Provide following services:

• Layout (physical implementation) of digital IC: RTL to GDSII
• Physical verification
• Timing and power analysis
• Design for test solutions: setup test concept, DFT insertion, test vector generation, low power ATPG, hierarchical test: core isolation, pattern retargeting, LBIST, scan compression: XOR, EDT
• RTL and Timing Constraint validation.
• Synthesis and Logic Equivalence Check.
• FPGA Design and Implementation
• Ramp up of young engineer, start-up teams

Onsite and remote support of a customer from Automotive, Aerospace and Defence and Telecommunication market. VHDL design, Synthesis, Static timing analysis (STA), DFT (scan insertion, xor compression, stuck-at and at-speed ATPG), Floorplan, CTS, timing closure, Place & Signal and power Route, IRDrop analysis and optimization of complex device at High Radiation(Space) technology, supervision of layout process implemented by subcontractor teams.

• EDA tools: Design Compiler, PrimeTime of Synopsys, Modelsim, Tessent of Mentor, RTL Compiler, Encounter Test, EDI of Cadence HiDFT-Signoff of Defacto

• Design and implementation of Hardware Programmable Components for Medical devices such as Computer tomography.
• VHDL coding from spec
• RTL verification and optimization for Xilinx FPGA and CPLD technologies.
• Formal Verification and RTL quality check.
• Adaptation of an old code to new spec and technology requirement
• Validation of FPGA and CPLD implementation in lab.
• EDA tools: ISE of Xilinx, HDL-Designer of Modelsim, Conformal LEC of Cadence

• Testability analysis of complex Digital TV design
• Stuck-at and at-Speed Automatic Test Pattern Generation (ATPG)
• Test coverage improves and test vector amount reduction
• EDA tools used: Encounter Test and Ncsim of Cadence.

• Project management: schedule and Statement of Work (SOW) definition and monitoring.
• Technical lead of flat (one man), and hierarchical (multi engineers) designs. Work in international teams (3-6 engineers) with colleagues from Russia, Israel, China, India and Europe.
• Physical implementation: RTL-synthesis trough Place and Route Layout implementation to Physical Verification and Tape-out to foundry of high-performance and ultra-low-power SOC devices at 180nm - 65nm technologies, for various customers from Russia, Israel and Europe.
• Design for Test (DFT) expert
• Customer relationship:
  
  • Methodology and design environment setup
  • Ramp-up customer team to work with Cadence tools on IC digital design implementation, know-how transfer
• Trainings for both customer and internal teams on:
  RTL Compiler, SOC Encounter, Encounter Test, Conformal Logic Equivalence Check, with cooperation of Education Department of Cadence.
• EDA tools used: RTL Compiler, SOC Encounter, Celtic NDC, Fire and Ice (QX/QRC), ETS, Power Meter, Voltage Storm, Encounter Test, NCsim, Conformal Constraint Design, Conformal Logic Equivalence Check , PVS of Cadence.

• Technical lead.
• Layout of complex high speed (1 GHz) SOC designs with LVDS driver and receivers at LSI Logic 180nm technology, with Synopsys and LSI Logic tools, for a customer from Super Computer market in UK.
• DFT service: scan-chain and Jtag insertion, stuck-at ATPG and Iddq generation and simulation.
• FPGA design with Xilinx SpartanII technology
• EDA tools used: Design Compiler, DFT Compiler, Prime Time, VCS, Jupiter/Apollo of Synopsys, V-system of Mentor, FlexStream of LSI Logic, Handle-C of Celoxica, Xilinx Project Navigator, Synplicity, FPGA Express of Synopsys

• Technical lead.
• Distributor of NEC and Chip Express ASIC vendors in Israel.
• Front-end services: RTL validation and synthesis, scan-chain and Jtag insertion, stuck-at ATPG and Iddq generation and simulation, preparation for layout.
• VHDL coding from spec. for Telecommunication and Medicine clients.
• ASIC to ASIC conversion from old to most recent ChipExpress technology
• Customer trainings, and flow setup.
• EDA tools used: Design Compiler, Primetime, VCS of Synopsys. Debussy of Novas, DFT tools of Syntest, Data Book (Escalade), Visual HDL (Innoveda), V-system of Mentor, OpenCAD of NEC, check_all of ChipExpress.

• Distributor of Chip Express ASIC vendors in Israel
• Front-end services: RTL validation and synthesis, scan-chain and Jtag insertion, stuck-at ATPG and Iddq generation and simulation, preparation for layout.
• FPGA to ASIC conversion from Xilinx and Altera to ChipExpress technology.
• EDA tools used: Leonardo of Exemplar, VCS of Viewlogic, DFT tools of Syntest, check_all of ChipExpress.