Freelancer: Hard- & Softwareentwickler f�r Embedded Systeme (ASIC/FPGA)

Freiberufler / Selbstst�ndiger

Remote-Arbeit

Verf�gbar ab: 01.07.2024

Verf�gbar zu: 100%

davon vor Ort: 90%

Top-Skills

ASIC, FPGA

VHDL, Verilog, SystemVerilog, SystemC, Embeded (C/C++)

Sprachen

English

German

Einsatzorte

L�nder

Deutschland, Schweiz, �sterreich

Remote-Arbeit

m�glich

Projekte

1 Jahr 2 Monate

2022-11 - 2023-12

HPP (High Protection Processor) military airborne communication system

FPGA HW/SW Engineer Xilinx Vivado/Vitis VHDL-2008 Motorola 68020 ...

Rolle

FPGA HW/SW Engineer

Projektinhalte

- Introduction into Motorola QUICC M68360 microcontroller
- Introduction into CPU32+ (Motorola 68020 compatible) processor code
- Implementation of few instructions so that the previous MC68000 implementation gets compatible with CPU32+ processor core (MC68020)
- Testing of the added instructions with short assembler sequences
- PicoRV32 RISC-V processor core for peripheral IP's control
- Xilinx MicroBlaze RISC processor core for peripheral IP's control
- Motorola IMB to AXI4 full bridge implementation in VHDL-2008
- Implementation of remaining IP's required, DualPort-RAM communication between CPU32+ and RISC processor, Top-Level and System Memory (using on chip BRAM) in VHDL-2008
- VHDL Testbench setup so that full system can be simulated (including booting the CPU32+ with ROM binary in SREC format)
- Write Firmware for the RISC processors using C/C++ to drive peripheral IP's to be compatible with original SW implementation running on not described RISC processor core used in QUICC chip (Interrupt driven driver for DMA, UART, SPI)
- gcc toolchain setup incl. newlib for M68K and RISC-V (RV32I) processor family
- RTL Synthesis and Implementation using Xilinx/AMD Vivado 2023.1
- Investigation and debugging on ZCU102 evaluation board
- CPU32+ Debugging using Lauterbach Power debugger
- MicroBlaze debugging using Vitis (TCF) debugger
- RTL code Linting and CDC using Aldec ALINT
- asks/Bugs tracking using JIRA
- Documentation (IODRAW)
- Revision control using git + TortoiseGit on Windows

Kenntnisse

Xilinx Vivado/Vitis VHDL-2008 Motorola 68020 RISC-V MicroBlaze ZCU102 Aldec Riviera C/C++ DMA UART SPI

Kunde

Rohde & Schwarz

Einsatzort

Remote/M�nchen

7 Monate

2022-12 - 2023-06

Linux IPC (Inter Process Communication) SW task acceleration by moving the execution to the HW in ARM multiprocessor system

HW/SW Engineer gem5 VS Code Linux Kernel ...

Rolle

HW/SW Engineer

Projektinhalte

- Porting of the whole environment previously developed in cooperation with TU Munich as part of PhD thesis to the Huawei environment
- Introduction into Gem5 system-level and processor simulation system
- Introduction into Huawei and TUM setup using different ARM processor models and CPU cluster setups, different Linux Kernel (4.14 vs 5.10) versions used and Glibc (2.27 vs 2.31) SW versions
- Add tracing points into Linux and apps/glibc code
- Linux kernel compile and creation of bootscripts to run different benchmarks
- Running different benchmarks (e.g. lib_test, ferret, parsec, epoll, eventfd etc.) in SW and repeat the same afterwards with enabled IPC HW accelerator
- Python and bash scripting for profiling and visualization of different runs/parameters between both SW/HW runs (e.g. creating plots using Python mathplot lib)
- Debugging the IPC HW accelerator Gem5 model and Linux driver for IPC accelerator, adding new C/C++ code portions as required due to different Linux kernel versions
- Configuration management using Git
- Documentation / User Manual for setting up the whole environment and execution/graphical evaluation of benchmark results

Produkte

ARM processor modeling

Kenntnisse

gem5 VS Code Linux Kernel IPCop Benchmarking Python C/C++

Kunde

HUAWEI

Einsatzort

Remote/Grenoble France

7 Monate

2022-03 - 2022-09

Design and initial verification of APIX3 embedded Display Port deserializer automotive ASIC - INAP566RAQ

ASIC Design SystemVerilog DisplayPort Python

Rolle

ASIC Design

Projektinhalte

- Excel Sheet preparation including complete PAD and IO description for functional/test/boot modes
- Python scripting for automatic Top-Level and several submodules (SystemVerilog) code generation (data extraction from .csv file, handling of different lists for each purpose, code templates using Python ?Templite? etc.)
- Excel Sheet preparation for ?APIX3? and ?embedded Display Port? analog PHY shield used for SCAN, IDDQ and BURN-IN test modes
- Python scripting for automatic analog PHY DFT shield submodule (SystemVerilog) code generation
- RTL coding using SystemVerilog, SystemVerilog Interfaces, ModPorts
- Top Level maintenance, integration of new modules into Top Level
- Design LINT checks using Realintent Ascent Lint
- Initial RTL Design Compile/Simulations using Cadence Xcelium Simulator to verify autogenerated code using simple SystemVerilog Testbench
- General understanding about interfacing, instantiation and setup/SW programming of TRILINEAR Embedded Display Port (eDP 1.4b) transmitter IP v 5.9.2
- Configuration management using Mercurial SCM (hg)
- Documentation / Top-Level Block Diagram (IODRAW)

Produkte

Automotive DisplayPort Serializer/Deserializer ASIC

Kenntnisse

SystemVerilog DisplayPort Python

Kunde

Inova Semiconductors

Einsatzort

Remote/M�nchen

1 Jahr 9 Monate

2020-07 - 2022-03

V93000 advanced chip tester system FPGA HW and SW development

FPGA HW and SW Designer Xilinx Vivado/Vitis Cadence Xcelium Cadence JasperGold ...

Rolle

FPGA HW and SW Designer

Projektinhalte

HW (PL) development:
- RTL design using SystemVerilog, SystemVerilog Interfaces
- Top Level maintinance, integration of new modules into Top-Level
- Clock Domain Crossing design checks using Cadence JasperGold CDC (v2020.06)
- Design Lint checks using Cadence JasperGold SuperLint (v2020.06)
- RTL Design Simulations/Debugging using Cadence Xcelium Simulator/SimVision Waveform Viewer/Schematic Tracer
- Instantiate XADC IP and IP configuration
- maintaining Block Diagram and module top level
- Development of new IP?s (Advantest Quartz bus <-> AXI bridge)

- FPGA Implementation using Vivado 2020.1

SW development:
- FreeRTOS introduction (task creation mechanism, task lists, queues, scheduler, ...)
- porting of existing Vivado/SDK 2017.4 project to Vivado/Vitis 2020.1 (HW and SW project, PL IP's and SW libraries)
- adapting the third patty IP SW libraries to newest version, customization to customer needs (freertos10_xilix_v1_6, lwip211_v1_2, standalone_v7_2)
- debug the issue with static variables stored in .bss section not initialized with '0'
- update the 'C' application with fix for .bss initialization, update linker script
- synchronization and processing alignment between two ARM cores using shared memory flags
- debbugung using Vitis built in debugger (expression breakpoint on read/write access, etc.)
- bootgen setup and boot .bin file generatinon, FSBL settings and issue solving
- optimize C code implementation using function pointers, variadic macros, etc.
- FSBL debugging due to QSPI FLASH boot issues (multicore boot, booting Core0 and Core1)
- File managment using SVN
- NVM driver (FLASH, EEPROM) and DAC/ADC driver extension to support own (Quartz/Nepomuk) chip communication bus
- add new driver for AXI IIC EEPROM accesses
- write new driver for Microchip Ethernet switch configuration over SPI and MDIO
- new driver for internaly developed "Sakura/Quartz" bus

Produkte

Chip Tester

Kenntnisse

Xilinx Vivado/Vitis Cadence Xcelium Cadence JasperGold FreeRTOS Xilinx Zynq 7020 Xilinx Kintex Ultrascale+ UART I2C

Kunde

Advantest

Einsatzort

B�blingen/Remote

1 Jahr 8 Monate

2018-10 - 2020-05

Surround View visualization system for automotive purpose

System Architect/FPGA Architect/FPGA & SW Designer MIPI CSI-2 Video Processing XAZU34EG ...

Rolle

System Architect/FPGA Architect/FPGA & SW Designer

Projektinhalte

HW (PL) development:
- Investigation of memory bandwidth issues on Micron LPDDR4 using ATG (AXI Traffic Generator) and built in APM (AXI Performance Monitor)
- Partial Configuration setup using AVNET Ultra96 and MAGNA Hydra2E development board
- Physical constraining for partial reconfiguration regions definition with .xdc constraints file
- System Architecture definition using Enterprise Architect (using previous project as template)
- FPGA Architecture definition according to the customer requirements
- Interface to the HW team for the PCB board features definition
- Introduction into MIPI CSI-2 v1.1, v1.2 and v2.0 interface protocol specification
- Write specification for Video Input Interface/Mip-Mapping implementation
- Implementation of input stage using MIPI CSI-2 RX/TX subsystem Xilinx IP (+ IP configuration)
- RTL coding of Video Input Interface module (6 x AXI-Stream -> AXI-Full MM) using VHDL-2008
- RTL coding of image Mip-Mapping algorithm using VHDL-2008
- RTL coding of Video input interface to provide data in format needed by MALI400 GPU (using color space conversion YCbCr to ARGB8888/RGB565) using VHDL-2008
- Introduction into Xilinx XPM_FIFO_SYNC, XPM_FIFO_ASYNC primitive configuration options (mem type, read mode, adv features, ...), DSP48 used as multiplier
- Setup SystemVerilog Testbench using Xilinx AXI-VIP as AXI-Lite Master for register configuration and AXI-Full Slave for protocol checking
- Writing short algorithms for the proof of the Mip-Mapping concept using Matlab & Octave
- Design implementation using Xilinx Vivado, SDK and HLS 2018.3 & 2019.1
- Verification (simulation runs) & scripting using Mentor Graphics QuestaSim 2019.3 and Xilinx Vivado (ISIM) 2018.3 & 2019.1
- Timing constraining (clocks, input/output delays, false paths, ...) with .xdc constraints file
- Synthesis using Xilinx Vivado, Synopsys Synplify and Mentor Graphich Precision Synthesis
- Lint checking using Synopsys Spyglass
- IBIS file extraction out of Vivado project needed for the HW team for PCB PSpice simulations
- System level integration of the own designed IP and Xilinx IP's into the final setup
- Test setups preparation (using different Xilinx IP's as VTPG, VTC, MIPI RX/TX, VDMA,
VID_IN_AXIS, AXIS_VID_OUT, AXIS_SUBSET_CONVERTER, GPIO, IIC)
- Hardware integration and ECU bring-up activities (FPGA setup, configuration of Sony MIPI/GVIF2 serializer/deserializer via GPIO/IIC)
- Measurements on MIPI D-PHY input and output with Oscilloscope using analog probes/built in MIPI protocol decoder

- FPGA internal real time debugging using System ILA IP core (also on AXIS and AXI-MM interfaces)�

SW development:

- Write several short C applications needed for DDR4 memory bandwidth investigation (Xilinx SDK)
- Write C++ application used for SW initiated partial reconfiguration and time measurements using Xilinx C++ PCAP and TTC library
- Writing bare metal app for initialization of all Xilinx IP's used in test setup (using Xilinx library)
- Coding of I2C interrupt driven routine for writing/reading different sizes of address/data bytes with ?C?
- Debugging of bare metal app, memory dump and performance analysis on all for A53 ARM cores (CPU utilization, instr. per cycle, L1 data cache accesses, CPU R/W stall cycles) using Xilinx SDK

- Maintenance of .xml project files

Other tasks:

- Configuration management using PTC Integrity 11
- Documentation using MS-Word, MS-Excel and MS-Visio, presentations setup with MS PowerPoint
- Introduction into image processing (Debayering, Tone-Mapping, Soebel-Filter, Alpha-Blending)
- Introduction into functional safety ASIL-B and ISO 26260
- Introduction into ONSEMI 1/2.5-Inch CMOS Digital Image Sensor AR0233AT, AS0149AT
(blanking time size, imager TPG, frame synchronized mode, I�C imager configuration, etc.)
- Configuration of OnSemi imager sensor (AS0149AT) to use external frame synchronization
- Introduction into Python, write several scripts needed for verification using Python
- Introduction into Testbench regression methodology using VUNIT
- Introduction into Xilinx VITIS unified software platform (2019.2)
- Continuous alignment with OnSemi and Xilinx FAE about issues found and design optimization

Produkte

Xilinx Vivado Mentor QuestaSim

Kenntnisse

MIPI CSI-2 Video Processing XAZU34EG XAZU4EG SystemVerilog VHDL-2008 LPDDR4 ISO26262 ASIL-B Partial-Reconfiguration Python Image Sensors (AR0149AT) ARM A53

Kunde

Magna Electronics

Einsatzort

Aschaffenburg/Remote

5 Monate

2018-04 - 2018-08

Design of high speed video processing for the high speed line camera for industrial applications

FPGA/SW development Xilinx Zynq Ultrascale+ MPSoC DDR4 AXI4-Interface (Master/Slave) ...

Rolle

FPGA/SW development

Produkte

Xilinx Vivado

Kenntnisse

Xilinx Zynq Ultrascale+ MPSoC DDR4 AXI4-Interface (Master/Slave) Memory bandwidth investigations ZCU102

Einsatzort

Konstanz

5 Monate

2017-10 - 2018-02

Design of power control and high-speed serial interfacing implementation within Xilinx Zynq XC7Z020 device for satellite testing application

FPGA designer Xilinx Vivado Xilinx Zynq 7000 SoC Enclustra Mars ZX3 FPGA module

Rolle

FPGA designer

Projektinhalte

HW development
- VHDL coding, verification, constraining and implementation using Xilinx Vivado 2017.3
- introduction into Xilinx Zynq SoC-FPGA device series
- introduction into Enclustra Mars ZX3 SO-DIMM FPGA module
- introduction into Enclustra MARS PM3 motherboard for Mars ZX3 SO-DIMM module
- SFP optical module high speed interface (using comma-free coded symbols) and control block VHDL coding
- module register and BRAM interfacing to AXI bus for connection with ARM processing system (PS)
- creating IP for reuse in block diagram and different configuration parameters using IP packager
- high speed interfacing using LVDS buffer and constraining within .xdc file
- testbench VHDL coding and implementation of different self-checking scenarios
- writing timing constraints, synthesis and implementation runs, timing fixcture
- create top level block diagram using ARM processing system(PS), different IP's from Xilinx and own IP's previously created with IP packager
- processing system (PS) configuration (graphical customization) and configuration of hard coded IP's and coresponding peripheral I/O pin mapping to MIO/EMIO banks
- configuration and debugging of internal signals on real implemented HW using chipscope (ILA hardware manager)
- measurements and failure search using Tektronix MSO5204B oscilloscope

SW development
- exporting HW configuration and AXI bus address mapping (HW description .xml file) to Xilinx SDK
- creating device driver (device tree .dts/.dtb files) in order to get new IP's accessible by already available Yocto Linux build made for Enclustra eval board
- creating BOOT.bin file including FSBL, Uboot, Linux image, device tree for QSPI flash and SDCARD using Xilinx SDK
- implement new interrupt service routine due to changed HW interrupt implementation using C++, compilation and debbuging with Xilinx SDK

- documentation using MS Word, Excel and Visio

Kenntnisse

Xilinx Vivado Xilinx Zynq 7000 SoC Enclustra Mars ZX3 FPGA module

Kunde

Siemens CVC/ATOS Austria

Einsatzort

Austria/Vienna

6 Monate

2017-04 - 2017-09

Participation in design of virtual prototype (VP) model and PS/FW verification of 3G Modem IP for IoT applications

SystemC C++ ARM7

Projektinhalte

Simulation setup and debugging SystemC VP models/regression runs using Synopsys Comet/Meteor
FW debugging executed on ARM7 processor core using Lauterbach T32 debugger
Debugging SystemC Models using Eclipse and gdb/ddd in Linux environment
Configuration management and configuration specification maintenance using IBM ClearCase, GIT

Produkte

Lauterbach T32 Eclipse Linux gdb/ddd ClearCase

Kenntnisse

SystemC C++ ARM7

Kunde

INTEL Deutschland

Projektinhalte

Clock/Reset/Power Management (MODCU) unit RTL design and verification using VHDL/Verilog
Test requirement setup with HP-ALM (Application Lifecycle Management) for MODCU verification
Debugging MODCU AHB-Slave interface after instantiating in Top-Level
Module level SystemVerilog testbench setup including AHB bus widget model
Generation of Register description .xml file using AMD Socrates-Essence Tool and RTL register (TOPSPIN) module generation
Setup module level System Verilog tescases according the requirements defined in HP-ALM
Debug the issues found with the System Verilog testcases and update RTL code accordingly
Setup System Verilog Assertions (SVA) into the testbench in order to automatically check different clock/reset/FSM modes of operation and clock division ratios depending on register settings and FSM power modes independently of currently executed testcase
FSM update for power/debug/reset modes of operation required for Synopsys ARC processor core
Update reset unit submodule to handle different reset sources (SW reset/Watchdog timer/external)
Implementation of 32-Bit Wish-Bone (WB) to AHB-Lite bus bridge in Verilog
Class-Based verification environment setup (Testbench including Wish-Bone(WB) Bus Master model and different testcases) using SystemVerilog
Clock gating, DFT, Spyglass checks, code coverage, testcase regressions, ECO fixes
Documentation, version management using Clearcase and GIT

Kunde

INTEL Deutschland

4 Monate

2016-09 - 2016-12

Development of industrial BiSS-Line interface and implementation in Altera Cyclone V FPGA

Projektinhalte

Full implementation specification setup according to the customers’ requirements
Coding of the complete BiSS Line interface module (module register stage, 8b10b-decoder, serial interface, protocol engine with FSM, interrupt generator, serial register communication module and top-level integration) using VHDL
Class-Based verification environment setup (Testbench including Avalon Bus Master and different testcases) using SystemVerilog
Debugging and code coverage extraction using Mentor Modelsim
Synthesis, implementation and timing check for Altera Cyclone V FPGA (5CSEMA4U23C6) using Quartus Prime Edition 16.0
Simple C testcase register programing using ARM DS-5 tool suite
QSYS setup for FPGA fabric and ARM HPS using Avalon bridge (HPS2FPGA bridge)
Bit-File download into Terasic DE0-Nano-SoC development board and initial implementation validation using Tektronix MSO4034B oscilloscope

Kunde

CENTITECH/FRABA

3 Monate

2016-07 - 2016-09

Development of Virtual Prototypes (VP) for PS/FW verification of 4G modem for XG756 ASIC

Projektinhalte

coding of abstracted VP models/interfaces for communication between 4G UE and BS on protocol
stack (PS) level using SystemC/C++
updating the verification setup according the changes introduced in new chipset (4DL/2UL carriers)
FW debugging on multiple Tensilica (Cadence) processor cores using XTENSA-Explorer
Debugging SystemC VP models and testcases using Eclipse GUI and gdb under Linux
Documentation with Visio/Word

Kunde

INTEL India (home office)

4 Monate

2016-03 - 2016-06

Circuit design, schematic entry and PCB Layout for Automotive Mobility application

Projektinhalte

Two/four-layer PCB design with circuit design, schematic entry and PCB layout
EMI aspects
Length and impedance matching of USB hub differential pairs
Circuit design for automotive usage
Eagle 7.5.0

Kunde

GeoMobile GmbH

5 Jahre 10 Monate

2010-09 - 2016-06

Development of Virtual Prototypes (VP) for FW verification of next Modem Chipset-Generation ASIC for 2G/3G/4G mobile phone applications

Projektinhalte

Development of Virtual Prototypes (VP) for FW verification of next Modem Chipset-Generation ASIC for 2G/3G/4G mobile phone applications: XG626, XG636, XG706, XG716, XG726, SofIA LTE, XG736, XG748

coding of abstracted VP models for communication between 3G/4G UE and BS on protocol stack
level using SystemC/C++
simulation setup and debugging/regression using Synopsys Comet/Meteor/Virtualizer
adaptation of Perl scripts to enable regression on Abstracted System on internal tool (iRunner)
debugging SystemC/C++ Models using MS VC++ in Windows environment
debugging SystemC Models using Eclipse and gdb/ddd in Linux environment
debugging ARM11/Cortex R5/A5/Tensilica FW using C and Lauterbach T32/XTENSA Debugger
RTL(VHDL): SystemC Top Level Entity and internal signal connection mapping to VP top level
extraction and analysis of UMTS protocol traces needed for debugging using Mobile Analyzer
extraction and analysis of LTE FW traces needed for debugging using STTP tool
configuration management and configuration specification maintenance using IBM ClearCase, GIT
general 3G (UMTS/HSPA/DC-HSDPA/DC-HSUPA) and 4G (LTE, CA) knowledge
Synopsys Virtualizer

Kunde

INTEL Deutschland

Projektinhalte

Two-layer PCB design with circuit design, schematic entry and PCB layout
Altium Designer 13

Kunde

UNICEPT GmbH

5 Monate

2010-04 - 2010-08

Participation in verification of automotive microcontroller using SystemVerilog and OVM

Projektinhalte

Adaptation of existing Top Level SystemVerilog testcases for different IP’s to new specification e.g. SPI, LCD IF, FLASH, CLKGEN, RESETGEN, WDT, TIMER, ADC
Adaptation of existing Top Level assembler (V850 CPU) testcases for different IP’s
Writing new Top Level SystemVerilog and assembler (V850) testcases to test new IP’s
Debugging of failing testcases using Cadance IUS Simulator and Novas Verdi

Kunde

RENESAS/NEC Electronics Europe

3 Monate

2010-01 - 2010-03

Requirement specification setup for next generation automotive powertrain applications ASIC

Projektinhalte

Writing requirement specification for new module IP’s (μs Bus and MPI-Multi Processor Interface)
Writing FTS-Functional Target Specification for μs Bus and MPI interface using Framemaker
Investigation of “use cases” for each requirement for automotive purpose

Kunde

NEC Electronics Europe

Projektinhalte

Verilog RTL coding of SPI interface connected to MobileSemi SRAM Hardmacro (4kx32 and 8kx64)
Testbench coding for SPI interface verification including different operation modes (FSM)
Writing testcases for SPI interface verification and debugging
MEMORYBIST module insertion using Logicvision(Mentor) ETMemory
Run gate level simulation to check backannotaded SDF timing data
STIL production testpattern generation
Documentation with MS Visio and MS Word

Kunde

TES Electronic Solutions

5 Monate

2009-03 - 2009-07

Participation in verification of A400M aircraft engine control hardware implemented in Xilinx Virtex V FPGA

Projektinhalte

Writing VHDL testcases on module level using specification from DOORS and DO-254 norm
Testcases adaptation to top level using HDL-Designer and DOORS description comparison
Adapting top level testcases to check backannotaded SDF timing data
Debugging of failing testcases after RTL update
Setup new testcases to check new added features and issues found during design review
Regression run

Kunde

MTU

1 Jahr 7 Monate

2008-01 - 2009-07

Participation in verification of a graphic controller ASIC for mobile phone applications

Projektinhalte

Writing testcases to verify different picture resolutions and output interface formats
Debugging of failing testcases after RTL update
Running full regression on several machines and many thousands testcases
Preparing Excel sheet for regression maintenance and testcases status overview
Setup new testcases to check new added features and issues found during design review
Setup register test script using C++ (reading data from Excel sheet and generating register test automatically using IO march algorithm)
Run gate level simulations and fix gate level issues
Code coverage issues + merging of coverage data for all functional and test modes (merging of code coverage data generated by two different testbenches)
Documentation, application note setup and presentation (Microsoft Word, Visio, Excel and PPT)

Kunde

TOSHIBA Electronics Europe

4 Monate

2007-09 - 2007-12

Participation in design and verification of the keyboard controller for mobile phone Applications

Projektinhalte

Verilog implementation of direct key feature and dual clock FIFO to existing chip module
I²C protocol implementation (START, STOP conditions, general call), verification of I²C module
Equivalency and design rule checking with ATRENTA Spyglass
CDC (clock domain crossing) investigation with ATRENTA Spyglass
Debugging of failing testcases after RTL update
Setup new testcases to check new added features and issues found during design review
Documentation (timing diagram) and application note setup (MS Word and MS Visio)

Kunde

TOSHIBA Electronics Europe

Projektinhalte

Verilog implementation of all sub-modules for FM radio denoising system using Visual-Elite
Area optimisation for all modules including several versions using FF’s or RAM’s for large memories
Verilog Testbench and verification environment setup for each sub-module
RTL verification and debugging using Modelsim
Validation of implementation concept using Matlab
Top level integration and top-level verification, NLint (Code style) checking
Synthesis and implementation into Altera Stratix device using Quartus
General signal processing knowledge for digitalized FM radio

Kunde

SONY Deutschland

10 Monate

2006-05 - 2007-02

Participation in design and verification of Graphic acceleration ASIC with embedded DRAM and 64Bit processor core (MIPS derivate) for automotive purposes

Projektinhalte

DFT Simulation and adapting of STIL production testpattern for processor core (direct test)
Clock generator verification and code coverage issues
Reset generator verification and code coverage issues
Mode decoder verification and code coverage issues
Writing C (TX49 CPU) and Verilog testcases for verification
DFT Simulation and adapting of STIL production testpattern for processor core (scan test)
ISO TS issues (DFMEA verification sheets)
DFT Simulation of STIL production testpattern with backannotated timing (SDF)

Kunde

TOSHIBA Electronics Europe

09/2005-05/2006: Participation in design and verification of Digital/Analog Terrestrial and Cable (8VSB) TV receiver ASIC

Duration: 9 months

Tasks:

Rework of Monitor-Bus interface for real-time debugging purposes, synthesis and implementation on XILINX Spartan XC2S 100 FPGA (XILINX ISE, Synplicity Synplify Pro)
RTL design of QAM-SLICER module with VHDL (based on design specification and SystemC model)
Synthesis of the module on TSMC 0.13um library (with already existing synthesis scripts)
Updating RTL to reach timing requirements (160 MHz)
Functional SystemC co-verification on module level using QAM-SLICER SystemC model
Equivalency and design rule checking with ATRENTA Spyglass
Debugging on RTL and C++ (SystemC) Module

11/2004-08/2005: Participation in design of a 16-bit dashboard microcontroller ASIC

Duration: 10 months

Tasks:

RTL design and verification on module level with Verilog
Functional verification on module level using AHB bus model using SystemC verification library (SCV)
Formal verification on module level with Synopsys Formality
Assertion based verification using PSL on module level
IO March (register check) program specification and coding using C++/SystemC
Verification list setup (Excel)
Documentation with Framemaker

01/2004-10/2004: Participation in an AAC+SBR Decoder IP-Core development

Duration: 10 months

Tasks:

VHDL design and verification of two sub blocks (time to frequency domain conversion and inverse)
for AAC audio decoder (with SBR + DRM)
Coding of C/C++ models for verification and debugging
Synthesis and implementation in XILINX Virtex II Pro chip

04/2003-12/2003: Microcontroller with MIPS R3000 Core successor device project

Duration: 8 months

Tasks:

Synthesis scripts setup, constraining and synthesis of separate IPs
Top level integration and one chip bottom up synthesis (Design Compiler)
Constraining and SCAN insertion, ATPG pattern generation (Fastscan)
STA scripts setup, constraining and STA (Primetime)
Assembler/C Test cases adaptation to new chip and debugging (NC-Sim, XL)
STA scripts modification for AC timing verification (Primetime)
Verification list setup according to QS 9000 for SPI module
Setup of new test cases according to verification list and debugging of RTL sources (?C assembler programming, NC-Sim, Verilog-XL)
Documentation

01/2003-02/2003: MOST Data Link Layer

Duration: 2 months

Tasks:

Coding of three blocks for MOST Data Link Layer in SystemC
SystemC coding for debugging and verification environment, verification
Documentation

12/2001-12/2002: Microcontroller with MIPS R3000 Core for Automotive purposes

Duration: 13 months

Tasks:

ADC Controller functional and design specification setup
ADC Controller RTL designing in Verilog
ADC FSM (Finite State Machine) and ADC Top Level designing with Mentor Graphics HDL Designer
Scripts setup, constraining and synthesis of ADC Controller, UART, SPI and CAN modules
Script adaptation and synthesis of CPU core to achieve target speed
Finding solution for setup violations, constraining and synthesis (incremental compile) of CPU core
Bottom-Up Top-Level synthesis
Script setup and constraining for functional and SCAN mode of operation for STA (Primetime)
Pre- and Postlayout statical timing analysis for trial and final netlist
AC-Check sheets preparation, Primetime scripts setup and AC timing verification of EBIF, UART, I�C, CAN and SPI modules, Documentation
CMOS 0.25?m TC240C TOSHIBA technology knowledge

08/2001-11/2001: Reed-Solomon Decoder

Duration: 4 months

Tasks:

Introduction in FEC (Forward Error Correction) algorithms
VHDL design and verification of Key-Equation solver block with different algorithms (Berlekamp-
Massey and Euclidean Algorithm) using composite Galois Fields GF((2r)s)
Coding of C/C++ models for verification and debugging
Timing optimization and synthesis for XILINX FPGA
Documentation

12/2000-07/2001: 40 Gigabit Multiplexer project

Duration: 8 months

Tasks:

Boundary SCAN (JTAG) insertion, structural & behavioural VHDL coding
Verilog testbench coding for High-speed multiplexer (2.5 Gbit)
Module simulation with Modelsim (VHDL)
Gate-Level Verilog netlist simulation with Cadence NC-Sim (functional & timing verification with
backannotated SDF's)
Tester vector generation (Texas Instruments TimePilot3.0 environment)
Synthesis of coded boundary SCAN modules
STA and QTM model extraction for several modules with Primetime
Documentation with Framemaker
CMOS 0.18?m GS30TR Texas Instruments technology knowledge

09/2000-11/2000: Introduction and design of CORDIC algorithms for digital design

Duration: 3 months

Tasks:

Design of a configurable IP
Testbench and simulation in VHDL
Documentation using Word and Visio

06/1999-08/2000: Test and quality control of application SW and HW of industrial PCs

Duration: 15 months

Tasks:

Test of ADC-, DAC- and I/O- cards
CAN interface programming
Software tests (Visual Basic and Visual C++)

Aus- und Weiterbildung

4 Jahre 8 Monate

1994-10 - 1999-05

Electrical Engineering, Faculty: Industrial electronics

Diplom Ingenieur (FH), University of Applied Sciences Cologne, Gummersbach

Abschluss

Diplom Ingenieur (FH)

Institution, Ort

University of Applied Sciences Cologne, Gummersbach

Kompetenzen

Top-Skills

ASIC, FPGA VHDL, Verilog, SystemVerilog, SystemC, Embeded (C/C++)

Produkte / Standards / Erfahrungen / Methoden

ASIL-B

ClearCase

Eclipse

ISO26262

Video Processing

Computer skills

Operating systems:
Linux (always in usage)
Windows 8, 10 (always in usage)

Programing languages:
Assembler (PIC, 8051, AVR μC) (good)
Assembler (MIPS R3000, V850, ARM11) (good)
VHDL, Verilog (very good)
System Verilog (very good)
Embedded/VP C/C++, SystemC (very good)
Perl, TCL, C-Shell (good)

Documentation:
MS-Word (always in usage)
MS-Excel (always in usage)
MS-Visio (always in usage)
MS-Outlook (always in usage)
MS-Powerpoint (always in usage)
Adobe FrameMaker (very good)
Adobe Acrobat (good)

Version control:
CVS, SVN (very good)
IBM Rational ClearCase, GIT (very good)

Tools for IC/ASIC/FPGA Design Flows:
Altium Designer, Eagle (PCB Layout) (very good)
Matlab, Mathcad (good)
PSPICE, Hspice (basic knowledge)
Mentor Precision Synthesis (good)
Synplicity Synplify (very good)
Xilinx ISE Series, Plan Ahead (very good)
Altera Quartus Prime (good)
Mentor Graphics HDL Designer (very good)
Model Sim, Cadence IUS, VCS (very good)
Microsoft Visual C++, Lauterbach T32 (very good)
KEIL μC Compiler (good)
Codevision AVR C Compiler (very good)
Design Compiler, Primetime (very good)
Mentor Graphics Fastscan, Tetramax (good)
Novas Debussy, Verdi (good)
Formality (basic knowledge)
Spyglass (very good)
IBM DOORS, HP-ALM (good)

Betriebssysteme

Linux

MS-DOS

Unix

Windows

Programmiersprachen

C++

Perl

Python

SystemC

SystemVerilog

Tcl/Tk

VERILOG

VHDL

VHDL-2008

Datenkommunikation

AXI4-Interface (Master/Slave)

MIPI CSI-2

Hardware

Altera Cyclone V

ARM A53

ARM7

DDR4

Enclustra Mars ZX3 FPGA module

Image Sensors (AR0149AT)

LPDDR4

Memory bandwidth investigations

XAZU3EG

XAZU4EG

Xilinx Vivado

Xilinx Zynq 7000 SoC

Xilinx Zynq Ultrascale+ MPSoC

ZCU102

Berechnung / Simulation / Versuch / Validierung

Siemens ModelSim/QuestaSim

Synopsys VCS

Cadence Xcelium

Aldec Riviera

Design / Entwicklung / Konstruktion

gdb/ddd

Lauterbach T32

Partial-Reconfiguration

Einsatzorte

L�nder

Deutschland, Schweiz, �sterreich

Remote-Arbeit

m�glich

Projekte

1 Jahr 2 Monate

2022-11 - 2023-12

HPP (High Protection Processor) military airborne communication system

FPGA HW/SW Engineer Xilinx Vivado/Vitis VHDL-2008 Motorola 68020 ...

Rolle

FPGA HW/SW Engineer

Projektinhalte

Kenntnisse

Xilinx Vivado/Vitis VHDL-2008 Motorola 68020 RISC-V MicroBlaze ZCU102 Aldec Riviera C/C++ DMA UART SPI

Kunde

Rohde & Schwarz

Einsatzort

Remote/M�nchen

7 Monate

2022-12 - 2023-06

Linux IPC (Inter Process Communication) SW task acceleration by moving the execution to the HW in ARM multiprocessor system

HW/SW Engineer gem5 VS Code Linux Kernel ...

Rolle

HW/SW Engineer

Projektinhalte

Produkte

ARM processor modeling

Kenntnisse

gem5 VS Code Linux Kernel IPCop Benchmarking Python C/C++

Kunde

HUAWEI

Einsatzort

Remote/Grenoble France

7 Monate

2022-03 - 2022-09

Design and initial verification of APIX3 embedded Display Port deserializer automotive ASIC - INAP566RAQ

ASIC Design SystemVerilog DisplayPort Python

Rolle

ASIC Design

Projektinhalte

Produkte

Automotive DisplayPort Serializer/Deserializer ASIC

Kenntnisse

SystemVerilog DisplayPort Python

Kunde

Inova Semiconductors

Einsatzort

Remote/M�nchen

1 Jahr 9 Monate

2020-07 - 2022-03

V93000 advanced chip tester system FPGA HW and SW development

FPGA HW and SW Designer Xilinx Vivado/Vitis Cadence Xcelium Cadence JasperGold ...

Rolle

FPGA HW and SW Designer

Projektinhalte

- FPGA Implementation using Vivado 2020.1

Produkte

Chip Tester

Kenntnisse

Xilinx Vivado/Vitis Cadence Xcelium Cadence JasperGold FreeRTOS Xilinx Zynq 7020 Xilinx Kintex Ultrascale+ UART I2C

Kunde

Advantest

Einsatzort

B�blingen/Remote

1 Jahr 8 Monate

2018-10 - 2020-05

Surround View visualization system for automotive purpose

System Architect/FPGA Architect/FPGA & SW Designer MIPI CSI-2 Video Processing XAZU34EG ...

Rolle

System Architect/FPGA Architect/FPGA & SW Designer

Projektinhalte

- FPGA internal real time debugging using System ILA IP core (also on AXIS and AXI-MM interfaces)�

SW development:

- Maintenance of .xml project files

Other tasks:

Produkte

Xilinx Vivado Mentor QuestaSim

Kenntnisse

MIPI CSI-2 Video Processing XAZU34EG XAZU4EG SystemVerilog VHDL-2008 LPDDR4 ISO26262 ASIL-B Partial-Reconfiguration Python Image Sensors (AR0149AT) ARM A53

Kunde

Magna Electronics

Einsatzort

Aschaffenburg/Remote

5 Monate

2018-04 - 2018-08

Design of high speed video processing for the high speed line camera for industrial applications

FPGA/SW development Xilinx Zynq Ultrascale+ MPSoC DDR4 AXI4-Interface (Master/Slave) ...

Rolle

FPGA/SW development

Produkte

Xilinx Vivado

Kenntnisse

Xilinx Zynq Ultrascale+ MPSoC DDR4 AXI4-Interface (Master/Slave) Memory bandwidth investigations ZCU102

Einsatzort

Konstanz

5 Monate

2017-10 - 2018-02

Design of power control and high-speed serial interfacing implementation within Xilinx Zynq XC7Z020 device for satellite testing application

FPGA designer Xilinx Vivado Xilinx Zynq 7000 SoC Enclustra Mars ZX3 FPGA module

Rolle

FPGA designer

Projektinhalte

- documentation using MS Word, Excel and Visio

Kenntnisse

Xilinx Vivado Xilinx Zynq 7000 SoC Enclustra Mars ZX3 FPGA module

Kunde

Siemens CVC/ATOS Austria

Einsatzort

Austria/Vienna

6 Monate

2017-04 - 2017-09

Participation in design of virtual prototype (VP) model and PS/FW verification of 3G Modem IP for IoT applications

SystemC C++ ARM7

Projektinhalte

Simulation setup and debugging SystemC VP models/regression runs using Synopsys Comet/Meteor
FW debugging executed on ARM7 processor core using Lauterbach T32 debugger
Debugging SystemC Models using Eclipse and gdb/ddd in Linux environment
Configuration management and configuration specification maintenance using IBM ClearCase, GIT

Produkte

Lauterbach T32 Eclipse Linux gdb/ddd ClearCase

Kenntnisse

SystemC C++ ARM7

Kunde

INTEL Deutschland

Projektinhalte

Clock/Reset/Power Management (MODCU) unit RTL design and verification using VHDL/Verilog
Test requirement setup with HP-ALM (Application Lifecycle Management) for MODCU verification
Debugging MODCU AHB-Slave interface after instantiating in Top-Level
Module level SystemVerilog testbench setup including AHB bus widget model
Generation of Register description .xml file using AMD Socrates-Essence Tool and RTL register (TOPSPIN) module generation
Setup module level System Verilog tescases according the requirements defined in HP-ALM
Debug the issues found with the System Verilog testcases and update RTL code accordingly
Setup System Verilog Assertions (SVA) into the testbench in order to automatically check different clock/reset/FSM modes of operation and clock division ratios depending on register settings and FSM power modes independently of currently executed testcase
FSM update for power/debug/reset modes of operation required for Synopsys ARC processor core
Update reset unit submodule to handle different reset sources (SW reset/Watchdog timer/external)
Implementation of 32-Bit Wish-Bone (WB) to AHB-Lite bus bridge in Verilog
Class-Based verification environment setup (Testbench including Wish-Bone(WB) Bus Master model and different testcases) using SystemVerilog
Clock gating, DFT, Spyglass checks, code coverage, testcase regressions, ECO fixes
Documentation, version management using Clearcase and GIT

Kunde

INTEL Deutschland

4 Monate

2016-09 - 2016-12

Development of industrial BiSS-Line interface and implementation in Altera Cyclone V FPGA

Projektinhalte

Full implementation specification setup according to the customers’ requirements
Coding of the complete BiSS Line interface module (module register stage, 8b10b-decoder, serial interface, protocol engine with FSM, interrupt generator, serial register communication module and top-level integration) using VHDL
Class-Based verification environment setup (Testbench including Avalon Bus Master and different testcases) using SystemVerilog
Debugging and code coverage extraction using Mentor Modelsim
Synthesis, implementation and timing check for Altera Cyclone V FPGA (5CSEMA4U23C6) using Quartus Prime Edition 16.0
Simple C testcase register programing using ARM DS-5 tool suite
QSYS setup for FPGA fabric and ARM HPS using Avalon bridge (HPS2FPGA bridge)
Bit-File download into Terasic DE0-Nano-SoC development board and initial implementation validation using Tektronix MSO4034B oscilloscope

Kunde

CENTITECH/FRABA

3 Monate

2016-07 - 2016-09

Development of Virtual Prototypes (VP) for PS/FW verification of 4G modem for XG756 ASIC

Projektinhalte

coding of abstracted VP models/interfaces for communication between 4G UE and BS on protocol
stack (PS) level using SystemC/C++
updating the verification setup according the changes introduced in new chipset (4DL/2UL carriers)
FW debugging on multiple Tensilica (Cadence) processor cores using XTENSA-Explorer
Debugging SystemC VP models and testcases using Eclipse GUI and gdb under Linux
Documentation with Visio/Word

Kunde

INTEL India (home office)

4 Monate

2016-03 - 2016-06

Circuit design, schematic entry and PCB Layout for Automotive Mobility application

Projektinhalte

Two/four-layer PCB design with circuit design, schematic entry and PCB layout
EMI aspects
Length and impedance matching of USB hub differential pairs
Circuit design for automotive usage
Eagle 7.5.0

Kunde

GeoMobile GmbH

5 Jahre 10 Monate

2010-09 - 2016-06

Development of Virtual Prototypes (VP) for FW verification of next Modem Chipset-Generation ASIC for 2G/3G/4G mobile phone applications

Projektinhalte

Development of Virtual Prototypes (VP) for FW verification of next Modem Chipset-Generation ASIC for 2G/3G/4G mobile phone applications: XG626, XG636, XG706, XG716, XG726, SofIA LTE, XG736, XG748

coding of abstracted VP models for communication between 3G/4G UE and BS on protocol stack
level using SystemC/C++
simulation setup and debugging/regression using Synopsys Comet/Meteor/Virtualizer
adaptation of Perl scripts to enable regression on Abstracted System on internal tool (iRunner)
debugging SystemC/C++ Models using MS VC++ in Windows environment
debugging SystemC Models using Eclipse and gdb/ddd in Linux environment
debugging ARM11/Cortex R5/A5/Tensilica FW using C and Lauterbach T32/XTENSA Debugger
RTL(VHDL): SystemC Top Level Entity and internal signal connection mapping to VP top level
extraction and analysis of UMTS protocol traces needed for debugging using Mobile Analyzer
extraction and analysis of LTE FW traces needed for debugging using STTP tool
configuration management and configuration specification maintenance using IBM ClearCase, GIT
general 3G (UMTS/HSPA/DC-HSDPA/DC-HSUPA) and 4G (LTE, CA) knowledge
Synopsys Virtualizer

Kunde

INTEL Deutschland

Projektinhalte

Two-layer PCB design with circuit design, schematic entry and PCB layout
Altium Designer 13

Kunde

UNICEPT GmbH

5 Monate

2010-04 - 2010-08

Participation in verification of automotive microcontroller using SystemVerilog and OVM

Projektinhalte

Adaptation of existing Top Level SystemVerilog testcases for different IP’s to new specification e.g. SPI, LCD IF, FLASH, CLKGEN, RESETGEN, WDT, TIMER, ADC
Adaptation of existing Top Level assembler (V850 CPU) testcases for different IP’s
Writing new Top Level SystemVerilog and assembler (V850) testcases to test new IP’s
Debugging of failing testcases using Cadance IUS Simulator and Novas Verdi

Kunde

RENESAS/NEC Electronics Europe

3 Monate

2010-01 - 2010-03

Requirement specification setup for next generation automotive powertrain applications ASIC

Projektinhalte

Writing requirement specification for new module IP’s (μs Bus and MPI-Multi Processor Interface)
Writing FTS-Functional Target Specification for μs Bus and MPI interface using Framemaker
Investigation of “use cases” for each requirement for automotive purpose

Kunde

NEC Electronics Europe

Projektinhalte

Verilog RTL coding of SPI interface connected to MobileSemi SRAM Hardmacro (4kx32 and 8kx64)
Testbench coding for SPI interface verification including different operation modes (FSM)
Writing testcases for SPI interface verification and debugging
MEMORYBIST module insertion using Logicvision(Mentor) ETMemory
Run gate level simulation to check backannotaded SDF timing data
STIL production testpattern generation
Documentation with MS Visio and MS Word

Kunde

TES Electronic Solutions

5 Monate

2009-03 - 2009-07

Participation in verification of A400M aircraft engine control hardware implemented in Xilinx Virtex V FPGA

Projektinhalte

Writing VHDL testcases on module level using specification from DOORS and DO-254 norm
Testcases adaptation to top level using HDL-Designer and DOORS description comparison
Adapting top level testcases to check backannotaded SDF timing data
Debugging of failing testcases after RTL update
Setup new testcases to check new added features and issues found during design review
Regression run

Kunde

MTU

1 Jahr 7 Monate

2008-01 - 2009-07

Participation in verification of a graphic controller ASIC for mobile phone applications

Projektinhalte

Writing testcases to verify different picture resolutions and output interface formats
Debugging of failing testcases after RTL update
Running full regression on several machines and many thousands testcases
Preparing Excel sheet for regression maintenance and testcases status overview
Setup new testcases to check new added features and issues found during design review
Setup register test script using C++ (reading data from Excel sheet and generating register test automatically using IO march algorithm)
Run gate level simulations and fix gate level issues
Code coverage issues + merging of coverage data for all functional and test modes (merging of code coverage data generated by two different testbenches)
Documentation, application note setup and presentation (Microsoft Word, Visio, Excel and PPT)

Kunde

TOSHIBA Electronics Europe

4 Monate

2007-09 - 2007-12

Participation in design and verification of the keyboard controller for mobile phone Applications

Projektinhalte

Verilog implementation of direct key feature and dual clock FIFO to existing chip module
I²C protocol implementation (START, STOP conditions, general call), verification of I²C module
Equivalency and design rule checking with ATRENTA Spyglass
CDC (clock domain crossing) investigation with ATRENTA Spyglass
Debugging of failing testcases after RTL update
Setup new testcases to check new added features and issues found during design review
Documentation (timing diagram) and application note setup (MS Word and MS Visio)

Kunde

TOSHIBA Electronics Europe

Projektinhalte

Verilog implementation of all sub-modules for FM radio denoising system using Visual-Elite
Area optimisation for all modules including several versions using FF’s or RAM’s for large memories
Verilog Testbench and verification environment setup for each sub-module
RTL verification and debugging using Modelsim
Validation of implementation concept using Matlab
Top level integration and top-level verification, NLint (Code style) checking
Synthesis and implementation into Altera Stratix device using Quartus
General signal processing knowledge for digitalized FM radio

Kunde

SONY Deutschland

10 Monate

2006-05 - 2007-02

Participation in design and verification of Graphic acceleration ASIC with embedded DRAM and 64Bit processor core (MIPS derivate) for automotive purposes

Projektinhalte

DFT Simulation and adapting of STIL production testpattern for processor core (direct test)
Clock generator verification and code coverage issues
Reset generator verification and code coverage issues
Mode decoder verification and code coverage issues
Writing C (TX49 CPU) and Verilog testcases for verification
DFT Simulation and adapting of STIL production testpattern for processor core (scan test)
ISO TS issues (DFMEA verification sheets)
DFT Simulation of STIL production testpattern with backannotated timing (SDF)

Kunde

TOSHIBA Electronics Europe

09/2005-05/2006: Participation in design and verification of Digital/Analog Terrestrial and Cable (8VSB) TV receiver ASIC

Duration: 9 months

Tasks:

Rework of Monitor-Bus interface for real-time debugging purposes, synthesis and implementation on XILINX Spartan XC2S 100 FPGA (XILINX ISE, Synplicity Synplify Pro)
RTL design of QAM-SLICER module with VHDL (based on design specification and SystemC model)
Synthesis of the module on TSMC 0.13um library (with already existing synthesis scripts)
Updating RTL to reach timing requirements (160 MHz)
Functional SystemC co-verification on module level using QAM-SLICER SystemC model
Equivalency and design rule checking with ATRENTA Spyglass
Debugging on RTL and C++ (SystemC) Module

11/2004-08/2005: Participation in design of a 16-bit dashboard microcontroller ASIC

Duration: 10 months

Tasks:

RTL design and verification on module level with Verilog
Functional verification on module level using AHB bus model using SystemC verification library (SCV)
Formal verification on module level with Synopsys Formality
Assertion based verification using PSL on module level
IO March (register check) program specification and coding using C++/SystemC
Verification list setup (Excel)
Documentation with Framemaker

01/2004-10/2004: Participation in an AAC+SBR Decoder IP-Core development

Duration: 10 months

Tasks:

VHDL design and verification of two sub blocks (time to frequency domain conversion and inverse)
for AAC audio decoder (with SBR + DRM)
Coding of C/C++ models for verification and debugging
Synthesis and implementation in XILINX Virtex II Pro chip

04/2003-12/2003: Microcontroller with MIPS R3000 Core successor device project

Duration: 8 months

Tasks:

Synthesis scripts setup, constraining and synthesis of separate IPs
Top level integration and one chip bottom up synthesis (Design Compiler)
Constraining and SCAN insertion, ATPG pattern generation (Fastscan)
STA scripts setup, constraining and STA (Primetime)
Assembler/C Test cases adaptation to new chip and debugging (NC-Sim, XL)
STA scripts modification for AC timing verification (Primetime)
Verification list setup according to QS 9000 for SPI module
Setup of new test cases according to verification list and debugging of RTL sources (?C assembler programming, NC-Sim, Verilog-XL)
Documentation

01/2003-02/2003: MOST Data Link Layer

Duration: 2 months

Tasks:

Coding of three blocks for MOST Data Link Layer in SystemC
SystemC coding for debugging and verification environment, verification
Documentation

12/2001-12/2002: Microcontroller with MIPS R3000 Core for Automotive purposes

Duration: 13 months

Tasks:

ADC Controller functional and design specification setup
ADC Controller RTL designing in Verilog
ADC FSM (Finite State Machine) and ADC Top Level designing with Mentor Graphics HDL Designer
Scripts setup, constraining and synthesis of ADC Controller, UART, SPI and CAN modules
Script adaptation and synthesis of CPU core to achieve target speed
Finding solution for setup violations, constraining and synthesis (incremental compile) of CPU core
Bottom-Up Top-Level synthesis
Script setup and constraining for functional and SCAN mode of operation for STA (Primetime)
Pre- and Postlayout statical timing analysis for trial and final netlist
AC-Check sheets preparation, Primetime scripts setup and AC timing verification of EBIF, UART, I�C, CAN and SPI modules, Documentation
CMOS 0.25?m TC240C TOSHIBA technology knowledge

08/2001-11/2001: Reed-Solomon Decoder

Duration: 4 months

Tasks:

Introduction in FEC (Forward Error Correction) algorithms
VHDL design and verification of Key-Equation solver block with different algorithms (Berlekamp-
Massey and Euclidean Algorithm) using composite Galois Fields GF((2r)s)
Coding of C/C++ models for verification and debugging
Timing optimization and synthesis for XILINX FPGA
Documentation

12/2000-07/2001: 40 Gigabit Multiplexer project

Duration: 8 months

Tasks:

Boundary SCAN (JTAG) insertion, structural & behavioural VHDL coding
Verilog testbench coding for High-speed multiplexer (2.5 Gbit)
Module simulation with Modelsim (VHDL)
Gate-Level Verilog netlist simulation with Cadence NC-Sim (functional & timing verification with
backannotated SDF's)
Tester vector generation (Texas Instruments TimePilot3.0 environment)
Synthesis of coded boundary SCAN modules
STA and QTM model extraction for several modules with Primetime
Documentation with Framemaker
CMOS 0.18?m GS30TR Texas Instruments technology knowledge

09/2000-11/2000: Introduction and design of CORDIC algorithms for digital design

Duration: 3 months

Tasks:

Design of a configurable IP
Testbench and simulation in VHDL
Documentation using Word and Visio

06/1999-08/2000: Test and quality control of application SW and HW of industrial PCs

Duration: 15 months

Tasks:

Test of ADC-, DAC- and I/O- cards
CAN interface programming
Software tests (Visual Basic and Visual C++)

Aus- und Weiterbildung

4 Jahre 8 Monate

1994-10 - 1999-05

Electrical Engineering, Faculty: Industrial electronics

Diplom Ingenieur (FH), University of Applied Sciences Cologne, Gummersbach

Abschluss

Diplom Ingenieur (FH)

Institution, Ort

University of Applied Sciences Cologne, Gummersbach

Kompetenzen

Top-Skills

ASIC, FPGA VHDL, Verilog, SystemVerilog, SystemC, Embeded (C/C++)

Produkte / Standards / Erfahrungen / Methoden

ASIL-B

ClearCase

Eclipse

ISO26262

Video Processing

Computer skills

Operating systems:
Linux (always in usage)
Windows 8, 10 (always in usage)

Version control:
CVS, SVN (very good)
IBM Rational ClearCase, GIT (very good)

Betriebssysteme

Linux

MS-DOS

Unix

Windows

Programmiersprachen

C++

Perl

Python

SystemC

SystemVerilog

Tcl/Tk

VERILOG

VHDL

VHDL-2008

Datenkommunikation

AXI4-Interface (Master/Slave)

MIPI CSI-2

Hardware

Altera Cyclone V

ARM A53

ARM7

DDR4

Enclustra Mars ZX3 FPGA module

Image Sensors (AR0149AT)

LPDDR4

Memory bandwidth investigations

XAZU3EG

XAZU4EG

Xilinx Vivado

Xilinx Zynq 7000 SoC

Xilinx Zynq Ultrascale+ MPSoC

ZCU102

Berechnung / Simulation / Versuch / Validierung

Siemens ModelSim/QuestaSim

Synopsys VCS

Cadence Xcelium

Aldec Riviera

Design / Entwicklung / Konstruktion

gdb/ddd

Lauterbach T32

Partial-Reconfiguration

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