Fachlicher Schwerpunkt dieses Freiberuflers

Hard- & Softwareentwickler für Embedded Systeme (ASIC/FPGA)

verfügbar ab
01.06.2020
verfügbar zu
100 %
davon vor Ort
85 %
PLZ-Gebiet, Land

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Kontaktwunsch

Ich möchte bevorzugt für Projekte in diesen Einsatzorten kontaktiert werden.

Projekte

10/2018 - 05/2020

1 Jahr 8 Monate

Surround View visualization system for automotive purpose

Rolle
System Architect/FPGA Architect/FPGA & SW Designer
Einsatzort
Aschaffenburg
Kenntnisse

MIPI CSI-2

Video Processing

XAZU34EG

XAZU4EG

SystemVerilog

VHDL-2008

LPDDR4

ISO26262

ASIL-B

Partial-Reconfiguration

Python

Image Sensors (AR0149AT)

ARM A53

Produkte

Xilinx Vivado

Mentor QuestaSim

04/2018 - 08/2018

5 Monate

Design of high speed video processing for the high speed line camera for industrial applications

Rolle
FPGA/SW development
Einsatzort
Konstanz
Kenntnisse

Xilinx Zynq Ultrascale+ MPSoC

DDR4

AXI4-Interface (Master/Slave)

Memory bandwidth investigations

ZCU102

Produkte

Xilinx Vivado

10/2017 - 02/2018

5 Monate

Design of power control and high-speed serial interfacing implementation within Xilinx Zynq XC7Z020 device for satellite testing application

Rolle
FPGA designer
Kunde
Siemens CVC/ATOS Austria
Einsatzort
Austria/Vienna
Projektinhalte
HW development
- VHDL coding, verification, constraining and implementation using Xilinx Vivado 2017.3
- introduction into Xilinx Zynq SoC-FPGA device series
- introduction into Enclustra Mars ZX3 SO-DIMM FPGA module
- introduction into Enclustra MARS PM3 motherboard for Mars ZX3 SO-DIMM module
- SFP optical module high speed interface (using comma-free coded symbols) and control block VHDL coding
- module register and BRAM interfacing to AXI bus for connection with ARM processing system (PS)
- creating IP for reuse in block diagram and different configuration parameters using IP packager
- high speed interfacing using LVDS buffer and constraining within .xdc file
- testbench VHDL coding and implementation of different self-checking scenarios
- writing timing constraints, synthesis and implementation runs, timing fixcture
- create top level block diagram using ARM processing system(PS), different IP's from Xilinx and own IP's previously created with IP packager
- processing system (PS) configuration (graphical customization) and configuration of hard coded IP's and coresponding peripheral I/O pin mapping to MIO/EMIO banks 
- configuration and debugging of internal signals on real implemented HW using chipscope (ILA hardware manager)
- measurements and failure search using Tektronix MSO5204B oscilloscope
 
SW development
- exporting HW configuration and AXI bus address mapping (HW description .xml file) to Xilinx SDK
- creating device driver (device tree .dts/.dtb files) in order to get new IP's accessible by already available Yocto Linux build made for Enclustra eval board
- creating BOOT.bin file including FSBL, Uboot, Linux image, device tree for QSPI flash and SDCARD using Xilinx SDK
- implement new interrupt service routine due to changed HW interrupt implementation using C++, compilation and debbuging with Xilinx SDK
 
- documentation using MS Word, Excel and Visio
 
Kenntnisse

Xilinx Vivado

Xilinx Zynq 7000 SoC

Enclustra Mars ZX3 FPGA module

04/2017 - 09/2017

6 Monate

Participation in design of virtual prototype (VP) model and PS/FW verification of 3G Modem IP for IoT applications

Kunde
INTEL Deutschland
Projektinhalte
  • Simulation setup and debugging SystemC VP models/regression runs using Synopsys Comet/Meteor
  • FW debugging executed on ARM7 processor core using Lauterbach T32 debugger
  • Debugging SystemC Models using Eclipse and gdb/ddd in Linux environment
  • Configuration management and configuration specification maintenance using IBM ClearCase, GIT
Kenntnisse

SystemC

C++

ARM7

Produkte

Lauterbach T32

Eclipse

Linux

gdb/ddd

ClearCase

10/2016 - 03/2017

6 Monate

Participation in design/verification of Modem ASIC for IoT applications

Kunde
INTEL Deutschland
Projektinhalte
  • Clock/Reset/Power Management (MODCU) unit RTL design and verification using VHDL/Verilog
  • Test requirement setup with HP-ALM (Application Lifecycle Management) for MODCU verification
  • Debugging MODCU AHB-Slave interface after instantiating in Top-Level
  • Module level SystemVerilog testbench setup including AHB bus widget model
  • Generation of Register description .xml file using AMD Socrates-Essence Tool and RTL register (TOPSPIN) module generation
  • Setup module level System Verilog tescases according the requirements defined in HP-ALM
  • Debug the issues found with the System Verilog testcases and update RTL code accordingly
  • Setup System Verilog Assertions (SVA) into the testbench in order to automatically check different clock/reset/FSM modes of operation and clock division ratios depending on register settings and FSM power modes independently of currently executed testcase
  • FSM update for power/debug/reset modes of operation required for Synopsys ARC processor core
  • Update reset unit submodule to handle different reset sources (SW reset/Watchdog timer/external)
  • Implementation of 32-Bit Wish-Bone (WB) to AHB-Lite bus bridge in Verilog
  • Class-Based verification environment setup (Testbench including Wish-Bone(WB) Bus Master model and different testcases) using SystemVerilog
  • Clock gating, DFT, Spyglass checks, code coverage, testcase regressions, ECO fixes
  • Documentation, version management using Clearcase and GIT

09/2016 - 12/2016

4 Monate

Development of industrial BiSS-Line interface and implementation in Altera Cyclone V FPGA

Kunde
CENTITECH/FRABA
Projektinhalte
  • Full implementation specification setup according to the customers’ requirements
  • Coding of the complete BiSS Line interface module (module register stage, 8b10b-decoder, serial interface, protocol engine with FSM, interrupt generator, serial register communication module and top-level integration) using VHDL
  • Class-Based verification environment setup (Testbench including Avalon Bus Master and different testcases) using SystemVerilog
  • Debugging and code coverage extraction using Mentor Modelsim
  • Synthesis, implementation and timing check for Altera Cyclone V FPGA (5CSEMA4U23C6) using Quartus Prime Edition 16.0
  • Simple C testcase register programing using ARM DS-5 tool suite
  • QSYS setup for FPGA fabric and ARM HPS using Avalon bridge (HPS2FPGA bridge)
  • Bit-File download into Terasic DE0-Nano-SoC development board and initial implementation validation using Tektronix MSO4034B oscilloscope

07/2016 - 09/2016

3 Monate

Development of Virtual Prototypes (VP) for PS/FW verification of 4G modem for XG756 ASIC

Kunde
INTEL India (home office)
Projektinhalte
  • coding of abstracted VP models/interfaces for communication between 4G UE and BS on protocol
    stack (PS) level using SystemC/C++
  • updating the verification setup according the changes introduced in new chipset (4DL/2UL carriers)
  • FW debugging on multiple Tensilica (Cadence) processor cores using XTENSA-Explorer
  • Debugging SystemC VP models and testcases using Eclipse GUI and gdb under Linux
  • Documentation with Visio/Word

03/2016 - 06/2016

4 Monate

Circuit design, schematic entry and PCB Layout for Automotive Mobility application

Kunde
GeoMobile GmbH
Projektinhalte
  • Two/four-layer PCB design with circuit design, schematic entry and PCB layout
  • EMI aspects
  • Length and impedance matching of USB hub differential pairs
  • Circuit design for automotive usage
  • Eagle 7.5.0

09/2010 - 06/2016

5 Jahre 10 Monate

Development of Virtual Prototypes (VP) for FW verification of next Modem Chipset-Generation ASIC for 2G/3G/4G mobile phone applications

Kunde
INTEL Deutschland
Projektinhalte

Development of Virtual Prototypes (VP) for FW verification of next Modem Chipset-Generation ASIC for 2G/3G/4G mobile phone applications: XG626, XG636, XG706, XG716, XG726, SofIA LTE, XG736, XG748

  • coding of abstracted VP models for communication between 3G/4G UE and BS on protocol stack
    level using SystemC/C++
  • simulation setup and debugging/regression using Synopsys Comet/Meteor/Virtualizer
  • adaptation of Perl scripts to enable regression on Abstracted System on internal tool (iRunner)
  • debugging SystemC/C++ Models using MS VC++ in Windows environment
  • debugging SystemC Models using Eclipse and gdb/ddd in Linux environment
  • debugging ARM11/Cortex R5/A5/Tensilica FW using C and Lauterbach T32/XTENSA Debugger
  • RTL(VHDL): SystemC Top Level Entity and internal signal connection mapping to VP top level
  • extraction and analysis of UMTS protocol traces needed for debugging using Mobile Analyzer
  • extraction and analysis of LTE FW traces needed for debugging using STTP tool
  • configuration management and configuration specification maintenance using IBM ClearCase, GIT
  • general 3G (UMTS/HSPA/DC-HSDPA/DC-HSUPA) and 4G (LTE, CA) knowledge
  • Synopsys Virtualizer

07/2013 - 09/2013

3 Monate

Circuit design, schematic entry and PCB Layout for security mobile device

Kunde
UNICEPT GmbH
Projektinhalte
  • Two-layer PCB design with circuit design, schematic entry and PCB layout
  • Altium Designer 13

04/2010 - 08/2010

5 Monate

Participation in verification of automotive microcontroller using SystemVerilog and OVM

Kunde
RENESAS/NEC Electronics Europe
Projektinhalte
  • Adaptation of existing Top Level SystemVerilog testcases for different IP’s to new specification e.g. SPI, LCD IF, FLASH, CLKGEN, RESETGEN, WDT, TIMER, ADC
  • Adaptation of existing Top Level assembler (V850 CPU) testcases for different IP’s
  • Writing new Top Level SystemVerilog and assembler (V850) testcases to test new IP’s
  • Debugging of failing testcases using Cadance IUS Simulator and Novas Verdi

01/2010 - 03/2010

3 Monate

Requirement specification setup for next generation automotive powertrain applications ASIC

Kunde
NEC Electronics Europe
Projektinhalte
  • Writing requirement specification for new module IP’s (μs Bus and MPI-Multi Processor Interface)
  • Writing FTS-Functional Target Specification for μs Bus and MPI interface using Framemaker
  • Investigation of “use cases” for each requirement for automotive purpose

09/2009 - 12/2009

4 Monate

SPI interfaced low voltage TSSOP SRAM device ASIC

Kunde
TES Electronic Solutions
Projektinhalte
  • Verilog RTL coding of SPI interface connected to MobileSemi SRAM Hardmacro (4kx32 and 8kx64)
  • Testbench coding for SPI interface verification including different operation modes (FSM)
  • Writing testcases for SPI interface verification and debugging
  • MEMORYBIST module insertion using Logicvision(Mentor) ETMemory
  • Run gate level simulation to check backannotaded SDF timing data
  • STIL production testpattern generation
  • Documentation with MS Visio and MS Word

03/2009 - 07/2009

5 Monate

Participation in verification of A400M aircraft engine control hardware implemented in Xilinx Virtex V FPGA

Kunde
MTU
Projektinhalte
  • Writing VHDL testcases on module level using specification from DOORS and DO-254 norm
  • Testcases adaptation to top level using HDL-Designer and DOORS description comparison
  • Adapting top level testcases to check backannotaded SDF timing data
  • Debugging of failing testcases after RTL update
  • Setup new testcases to check new added features and issues found during design review
  • Regression run

01/2008 - 07/2009

1 Jahr 7 Monate

Participation in verification of a graphic controller ASIC for mobile phone applications

Kunde
TOSHIBA Electronics Europe
Projektinhalte
  • Writing testcases to verify different picture resolutions and output interface formats
  • Debugging of failing testcases after RTL update
  • Running full regression on several machines and many thousands testcases
  • Preparing Excel sheet for regression maintenance and testcases status overview
  • Setup new testcases to check new added features and issues found during design review
  • Setup register test script using C++ (reading data from Excel sheet and generating register test automatically using IO march algorithm)
  • Run gate level simulations and fix gate level issues
  • Code coverage issues + merging of coverage data for all functional and test modes (merging of code coverage data generated by two different testbenches)
  • Documentation, application note setup and presentation (Microsoft Word, Visio, Excel and PPT)

09/2007 - 12/2007

4 Monate

Participation in design and verification of the keyboard controller for mobile phone Applications

Kunde
TOSHIBA Electronics Europe
Projektinhalte
  • Verilog implementation of direct key feature and dual clock FIFO to existing chip module
  • I²C protocol implementation (START, STOP conditions, general call), verification of I²C module
  • Equivalency and design rule checking with ATRENTA Spyglass
  • CDC (clock domain crossing) investigation with ATRENTA Spyglass
  • Debugging of failing testcases after RTL update
  • Setup new testcases to check new added features and issues found during design review
  • Documentation (timing diagram) and application note setup (MS Word and MS Visio)

03/2007 - 08/2007

6 Monate

Participation in design and verification of digital FM radio denoising system

Kunde
SONY Deutschland
Projektinhalte
  • Verilog implementation of all sub-modules for FM radio denoising system using Visual-Elite
  • Area optimisation for all modules including several versions using FF’s or RAM’s for large memories
  • Verilog Testbench and verification environment setup for each sub-module
  • RTL verification and debugging using Modelsim
  • Validation of implementation concept using Matlab
  • Top level integration and top-level verification, NLint (Code style) checking
  • Synthesis and implementation into Altera Stratix device using Quartus
  • General signal processing knowledge for digitalized FM radio

05/2006 - 02/2007

10 Monate

Participation in design and verification of Graphic acceleration ASIC with embedded DRAM and 64Bit processor core (MIPS derivate) for automotive purposes

Kunde
TOSHIBA Electronics Europe
Projektinhalte
  • DFT Simulation and adapting of STIL production testpattern for processor core (direct test)
  • Clock generator verification and code coverage issues
  • Reset generator verification and code coverage issues
  • Mode decoder verification and code coverage issues
  • Writing C (TX49 CPU) and Verilog testcases for verification
  • DFT Simulation and adapting of STIL production testpattern for processor core (scan test)
  • ISO TS issues (DFMEA verification sheets)
  • DFT Simulation of STIL production testpattern with backannotated timing (SDF)

Projekthistorie

09/2005-05/2006: Participation in design and verification of Digital/Analog Terrestrial and Cable (8VSB) TV receiver ASIC

Duration: 9 months

Tasks:

  • Rework of Monitor-Bus interface for real-time debugging purposes, synthesis and implementation on XILINX Spartan XC2S 100 FPGA (XILINX ISE, Synplicity Synplify Pro)
  • RTL design of QAM-SLICER module with VHDL (based on design specification and SystemC model)
  • Synthesis of the module on TSMC 0.13um library (with already existing synthesis scripts)
  • Updating RTL to reach timing requirements (160 MHz)
  • Functional SystemC co-verification on module level using QAM-SLICER SystemC model
  • Equivalency and design rule checking with ATRENTA Spyglass
  • Debugging on RTL and C++ (SystemC) Module

11/2004-08/2005: Participation in design of a 16-bit dashboard microcontroller ASIC

Duration: 10 months

Tasks:

  • RTL design and verification on module level with Verilog
  • Functional verification on module level using AHB bus model using SystemC verification library (SCV)
  • Formal verification on module level with Synopsys Formality
  • Assertion based verification using PSL on module level
  • IO March (register check) program specification and coding using C++/SystemC
  • Verification list setup (Excel)
  • Documentation with Framemaker

01/2004-10/2004: Participation in an AAC+SBR Decoder IP-Core development

Duration: 10 months

Tasks:

  • VHDL design and verification of two sub blocks (time to frequency domain conversion and inverse)
    for AAC audio decoder (with SBR + DRM)
  • Coding of C/C++ models for verification and debugging
  • Synthesis and implementation in XILINX Virtex II Pro chip

04/2003-12/2003: Microcontroller with MIPS R3000 Core successor device project

Duration: 8 months

Tasks:

  • Synthesis scripts setup, constraining and synthesis of separate IPs
  • Top level integration and one chip bottom up synthesis (Design Compiler)
  • Constraining and SCAN insertion, ATPG pattern generation (Fastscan)
  • STA scripts setup, constraining and STA (Primetime)
  • Assembler/C Test cases adaptation to new chip and debugging (NC-Sim, XL)
  • STA scripts modification for AC timing verification (Primetime)
  • Verification list setup according to QS 9000 for SPI module
  • Setup of new test cases according to verification list and debugging of RTL sources (μC assembler programming, NC-Sim, Verilog-XL)
  • Documentation

01/2003-02/2003: MOST Data Link Layer

Duration: 2 months

Tasks:

  • Coding of three blocks for MOST Data Link Layer in SystemC
  • SystemC coding for debugging and verification environment, verification
  • Documentation

12/2001-12/2002: Microcontroller with MIPS R3000 Core for Automotive purposes

Duration: 13 months

Tasks:

  • ADC Controller functional and design specification setup
  • ADC Controller RTL designing in Verilog
  • ADC FSM (Finite State Machine) and ADC Top Level designing with Mentor Graphics HDL Designer
  • Scripts setup, constraining and synthesis of ADC Controller, UART, SPI and CAN modules
  • Script adaptation and synthesis of CPU core to achieve target speed
  • Finding solution for setup violations, constraining and synthesis (incremental compile) of CPU core
  • Bottom-Up Top-Level synthesis
  • Script setup and constraining for functional and SCAN mode of operation for STA (Primetime)
  • Pre- and Postlayout statical timing analysis for trial and final netlist
  • AC-Check sheets preparation, Primetime scripts setup and AC timing verification of EBIF, UART, I²C, CAN and SPI modules, Documentation
  • CMOS 0.25μm TC240C TOSHIBA technology knowledge

08/2001-11/2001: Reed-Solomon Decoder

Duration: 4 months

Tasks:

  • Introduction in FEC (Forward Error Correction) algorithms
  • VHDL design and verification of Key-Equation solver block with different algorithms (Berlekamp-
    Massey and Euclidean Algorithm) using composite Galois Fields GF((2r)s)
  • Coding of C/C++ models for verification and debugging
  • Timing optimization and synthesis for XILINX FPGA
  • Documentation

12/2000-07/2001: 40 Gigabit Multiplexer project

Duration: 8 months

Tasks:

  • Boundary SCAN (JTAG) insertion, structural & behavioural VHDL coding
  • Verilog testbench coding for High-speed multiplexer (2.5 Gbit)
  • Module simulation with Modelsim (VHDL)
  • Gate-Level Verilog netlist simulation with Cadence NC-Sim (functional & timing verification with
    backannotated SDF's)
  • Tester vector generation (Texas Instruments TimePilot3.0 environment)
  • Synthesis of coded boundary SCAN modules
  • STA and QTM model extraction for several modules with Primetime
  • Documentation with Framemaker
  • CMOS 0.18μm GS30TR Texas Instruments technology knowledge

09/2000-11/2000: Introduction and design of CORDIC algorithms for digital design

Duration: 3 months

Tasks:

  • Design of a configurable IP
  • Testbench and simulation in VHDL
  • Documentation using Word and Visio

06/1999-08/2000: Test and quality control of application SW and HW of industrial PCs

Duration: 15 months

Tasks:

  • Test of ADC-, DAC- and I/O- cards
  • CAN interface programming
  • Software tests (Visual Basic and Visual C++)

Kompetenzen

Programmiersprachen
C
C++
Perl
Python
SystemC
SystemVerilog
Tcl/Tk
VERILOG
VHDL
VHDL-2008

Betriebssysteme
Linux
MS-DOS
Unix
Linux
Windows

Sprachkenntnisse
English
German

Produkte / Standards / Erfahrungen
ASIL-B
ClearCase
Eclipse
ISO26262
Video Processing

Computer skills

Operating systems:
Linux (always in usage)
Windows 8, 10 (always in usage)

Programing languages:
Assembler (PIC, 8051, AVR μC) (good)
Assembler (MIPS R3000, V850, ARM11) (good)
VHDL, Verilog (very good)
System Verilog (very good)
Embedded/VP C/C++, SystemC (very good)
Perl, TCL, C-Shell (good)

Documentation:
MS-Word (always in usage)
MS-Excel (always in usage)
MS-Visio (always in usage)
MS-Outlook (always in usage)
MS-Powerpoint (always in usage)
Adobe FrameMaker (very good)
Adobe Acrobat (good)

Version control:
CVS, SVN (very good)
IBM Rational ClearCase, GIT (very good)

Tools for IC/ASIC/FPGA Design Flows:
Altium Designer, Eagle (PCB Layout) (very good)
Matlab, Mathcad (good)
PSPICE, Hspice (basic knowledge)
Mentor Precision Synthesis (good)
Synplicity Synplify (very good)
Xilinx ISE Series, Plan Ahead (very good)
Altera Quartus Prime (good)
Mentor Graphics HDL Designer (very good)
Model Sim, Cadence IUS, VCS (very good)
Microsoft Visual C++, Lauterbach T32 (very good)
KEIL μC Compiler (good)
Codevision AVR C Compiler (very good)
Design Compiler, Primetime (very good)
Mentor Graphics Fastscan, Tetramax (good)
Novas Debussy, Verdi (good)
Formality (basic knowledge)
Spyglass (very good)
IBM DOORS, HP-ALM (good)


Hardware
Altera Cyclone V
ARM A53
ARM7
DDR4
Enclustra Mars ZX3 FPGA module
Image Sensors (AR0149AT)
LPDDR4
Memory bandwidth investigations
XAZU3EG
XAZU4EG
Xilinx Vivado
Xilinx Zynq 7000 SoC
Xilinx Zynq Ultrascale+ MPSoC
ZCU102

Design / Entwicklung / Konstruktion
gdb/ddd
Lauterbach T32
Partial-Reconfiguration

Datenkommunikation
AXI4-Interface (Master/Slave)
MIPI CSI-2

Berechnung / Simulation / Versuch / Validierung
Mentor QuestaSim

Bemerkungen

ASIC
FPGA

DFT
Mikrokontroller

SoC

PCB Layout


Aus- und Weiterbildung

10/1994 - 05/1999

4 Jahre 8 Monate

Electrical Engineering, Faculty: Industrial electronics

Abschluss
Diplom Ingenieur (FH)
Institution, Ort
University of Applied Sciences Cologne, Gummersbach

Ausbildungshistorie

Design of a 3-phase PWM controller in VHDL

Duration: 6 months

practical thesis: 

  • Specification setup
  • RTL coding
  • Verification
  • Implementation in a XILINX FPGA
  • Validation and tests in a test environment
  • Documentation

Design of a PC keyboard controller for an industrial PC

Duration: 3 months

practical thesis: 

  • Implementation in 80C51 μController using Assembler
  • Documentation, flow chart

Design of a high resolution encoder controller for the evaluation of incremental sinus waveforms

Duration: 7 months

diploma thesis: 

  • Design and simulation in VHDL
  • Implementation in a XILINX Spartan FPGA
  • Validation and tests in a test environment
  • Documentation