Digitale Hardware/ASIC/FPGA Entwickler, Embedded Softwareentwickler
Aktualisiert am 15.12.2023
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Verfügbar ab: 15.12.2023
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FPGA design, Software development, ASIC-Design
Test Engineering
Deutsch
Verhandlungssicher
Englisch
Verhandlungssicher
Urdu
Muttersprache

Einsatzorte

Einsatzorte

Deutschland, Österreich, Schweiz

Großbritannien

nicht möglich

Projekte

Projekte

10 Monate
2023-06 - heute

Design and Simulation of an SDR-System

Consultant FPGA Development
Consultant FPGA Development
VHDL Xilinx UltraScale+ Zynq FPGA Vivado Riviera Pro Vunit
1 Jahr 9 Monate
2022-07 - heute

FPGA development

Consultant DSP and FPGA Development
Consultant DSP and FPGA Development
  • Worked on FPGA development of a highly innovative hand-held radar for weapons search
  • Hardware/Software distribution
  • Implementation of parts of DSP in FPGA
Verilog Xilinx UltraScale+ Zynq FPGA Vivado Modelsim MATLAB
Lassen Peak Inc.
4 Monate
2023-01 - 2023-04

Feasibility study for an image processing solution

FPGA-Design Engineer
FPGA-Design Engineer

  • Worked on feasibility study for an image processing solution
  • Evaluated different possibilities for the solution
  • Devised several solutions and simulated them in python to select an optimal one
  • Realized the same in VHDL 

VHDL Xilinx UltraScale+ Zynq FPGA Vivado Python
Alltec Laser/FOBA Laser
3 Jahre 10 Monate
2018-09 - 2022-06

FPGA development of an award-winning hand-held LIDAR

Consultant FPGA Development and Test
Consultant FPGA Development and Test

  • Worked on FPGA development of an award-winning hand-held LIDAR based 3D-Scanning system
  • Integrated Image sensors and other peripherals in the system
  • Realized a part of imaging pipeline in FPGA
  • Also developed a python test suit for the system level tests

VHDL Microsemi Polarfire FPGA Libero 12.1 Modelsim Python QT5 Linux C
Leica Geosystems AG
1 Jahr 7 Monate
2017-02 - 2018-08

?Space? department on development of a Solar Array Simulator

Consultant Hardware/Software Development VHDL ModelSim JavaScript ...
Consultant Hardware/Software Development

  • Worked in the ?Space? department on development of a Solar Array Simulator, used in verification and test of Satellite?s power system

VHDL ModelSim JavaScript SCPI Lab Equipment scrum XILIX ISE Modelsim Altium Designer Python
Siemens CVC GmbH
Wien
4 Monate
2017-03 - 2017-06

Development of a Gigabit-Ethernet Switch

Consultant in FPGA-Development Gigabit Ethernet AXI4-Stream AXI-Lite ...
Consultant in FPGA-Development

  • Worked on the development of a Gigabit Ethernet Switch as a part of a new concept of next generation high speed servers
  • It was used as a packet switch between a 40 Gb Ethernet on one side and 6 microprocessor cores, each connected with a 10 Gb Ethernet on the other side

Gigabit Ethernet AXI4-Stream AXI-Lite VHDL Python XILINX Vivado Questa Sim Xilinx Vivado Questa AMBA AXI4-Stream
Hybridserver Tec GmbH
Norderstedt
3 Monate
2016-11 - 2017-01

Embedded Software and "Skills" development for IoT and Cloud Applications

Consultant for Embedded Software Development for IoT Python ?Clinux Requirements Engineering ...
Consultant for Embedded Software Development for IoT

  • Worked on further development of their product WiButler
  • Worked on smart-home ?skill? development for Amazon-Echo

Python ?Clinux Requirements Engineering Django OAuth 2.0 Amazon AWS IoT-Device scrum JavaScript
IExergy GmbH
3 Jahre 1 Monat
2013-09 - 2016-09

Test and validation of a new generation of inverters

R&D Consultant for Verification and Validation
R&D Consultant for Verification and Validation

  • Worked on test and validation of a new generation of inverters (frequency converters). Inspected all its existing requirements for sanity and redundancy. Wrote requirements for ?undefined? parts of the system keeping international norms (like IEC 61131) in consideration. Suggested tests for those requirements. Carried them out and documented each test.
  • Worked specifically on ?encoder signal processing? and binary inputs/outputs by writing requirements, suggesting tests for those requirements and carrying out and documenting those tests during and after the development.
  • Developed and verified an SPI-based ?diagnosis interface? (using VHDL) for inverters to get and display the key parameters of inverter during its operation.
  • Introduced regression tests for hardware-software system testing. Developed a scripting framework for regression tests based on UDEDebugger?s COM interface, Quartus tcl interface, Perl scripting and Make files.
  • Introduced IP-XACT (metadata) based system design and documentation flow. Evaluated different off-the-shelf IPXACT tools on behalf of SEW but the developers were not happy with their end results. I ended up writing my own tool using extensive Python scripting. Both hardware and firmware development teams have readily accepted it. This tool takes IP-XACT description as input and generates Hardware Abstraction Layer (HAL) in C++, Register Interfaces in VHDL and html documentation of all memory mapped register. This tool has eliminated a major cause of faults in the design flow.
  • Worked on a system-tester based on a Cyclone-V board with Cortex-A9 cores and ?Clinux. Tested the board by writing simple drivers. Developed a web-service (SOAP) based interface between PC and the test board. 

Python C++ RE VHDL Quartus Modelsim ?Clinux Cyclone-V Arm Cortex-A9 IP-XACT oscilloscope logic analyzer TriCore UDE-Debugger COM SOAP
SEW Eurodrive GmbH & Co. KG
1 Jahr 1 Monat
2012-06 - 2013-06

Design, development and verification of a new field bus

R&D Consultant C C++ NIOS ...
R&D Consultant

  • Design, development and verification of a new field bus
  • The design was implemented on an FPGA development board
  • My responsibilities included development and verification of Layer 2 and 3 of the devised communication protocol of this new Ethernet-compatible field-bus

C C++ NIOS Perl DSP Lab instruments like oscilloscope and logic analyzer
Robert Bosch GmbH (Corporate Research)
1 Jahr 5 Monate
2011-01 - 2012-05

Digital IC Design

Consultant VHDL ModelSim Spyglass ...
Consultant

  • As a part of the IC-Design team I was involved in design and verification of  several LTE-Baseband chips
  • My activities involved RTL-coding for a given DSP algorithm, functional verification, linting and trial synthesis

VHDL ModelSim Spyglass Design Compiler AMBA Tensilica DSP FFT C
Intel Mobile Communications Dresden GmbH
2 Jahre 9 Monate
2008-05 - 2011-01

Processed the customers? C++/SystemC code

Corporate Application Engineer
Corporate Application Engineer

  • As a Corporate Application Engineer at ChipVision Design Systems, I had the responsibility to serve as an interface between customers and engineering team
  • As a part of my responsibility, I processed the customers? C++/SystemC code to perform high-level-synthesis with PowerOpt and verified the correctness of the generated RTL-Verilog by simulation

ChipVision Design Systems AG
5 Jahre 7 Monate
2005-07 - 2011-01

Software Developement

Corporate Application Engineer/ Senior Software Developer
Corporate Application Engineer/ Senior Software Developer

  • ChipVision Design Systems is an EDA(Electronic Design Automation) company, which has specialized in low-power high-level-synthesis
  • As Senior Software Developer I contributed towards development of this future oriented technology and as Corporate Application Engineer I contributed towards effective application of this technology by the customers

ChipVision Design Systems AG
1 Jahr
2007-05 - 2008-04

Programming of a Verilog-Writers

Senior Software Development Engineer C++ Verilog Icarus ...
Senior Software Development Engineer

  • ChipVision's high-level-synthesis tool PowerOpt outputs the RTL in Verilog
  • Special attention is given on the readability of the generated code
  • As a part of my work in the back-end group, I explored the forms of expression in Verilog, which express the structure of the generated circuit in a more readable fashion
  • Worked in a Scrum team to realize the Verilog-Writer

C++ Verilog Icarus Cadence RTL-Compiler Eclipse Scrum
ChipVision Design Systems AG
4 Monate
2007-01 - 2007-04

Requirements gathering for PowerOpt

EDA Development Engineer
EDA Development Engineer

  • ChipVision decided to bring out a high-level-synthesis tool in the beginning of 2007
  • Requirements gathering was obviously the the first step in the huge project ahead
  • At that phase, I interacted with two groups: Synthesis Kernel Group and Back-End-Group
  • I took part in brain storming sessions to capture the requirements for the new Product PowerOpt

ChipVision Design Systems AG
1 Jahr 6 Monate
2005-07 - 2006-12

LEMOS - Low-Power Design Methods for Mobile Systems

EDA Development Engineer Verilog C++ Qt Libaries ...
EDA Development Engineer

  • Mobile systems have special requirements on low power design methods
  • In this project, new methods for estimation and optimization of dissipation losses in the mobile systems were explored
  • As a part of this research project, I analyzed clock trees, which are highly critical networks with respect to dissipation losses
  • As a result of this research, new methods for estimation and optimization of dissipation losses were developed
  • I verified the developed models using Cadence's SoC Encounter
  • I integrated the source-code in ChipVision's estimation tool ORINOCO

Verilog C++ Qt Libaries SoC Encounter NC-Sim X-Graph Eclipse
ChipVision Design Systems AG
11 Monate
2004-08 - 2005-06

OSIS Compliant Measuring Head

System and Hardware Development Engineer C++ VHDL Altera Quartus ...
System and Hardware Development Engineer

  • OSIS is an emerging standard for the electromechanical and software interfaces of the measuring heads for coordinate measurement machines (CMMs)
  • The goal of the project was to integrate a higher resolution image sensor (LUPA4000) in the design and thereby considering all compliance guidelines from OSIS consortium
  • Digital high speed hardware (FPGA based) and embedded software development, PCB-Design and layout, System Integration and testing

C++ VHDL Altera Quartus Protel Analog Electronics MS Project
Hightronix GmbH
1 Jahr 6 Monate
2004-01 - 2005-06

Hardware Development Engineering

System and Hardware Development Engineer
System and Hardware Development Engineer

  • Worked on development of highly precise laser based 3D optical sensors for coordinate measurement machines
  • As a System and Hardware Development Engineer, I developed the concepts, realized them in Hardware and Software and tested and debugged the products until their production maturity

Hightronix GmbH
10 Monate
2004-06 - 2005-03

Dentascope with 2 synchronous optical 3D-Sensors

System and Hardware Development Engineer C++ VHDL Altera Quartus ...
System and Hardware Development Engineer

  • Dentascope was a compact and highly precise 3D Scanner, especially designed for applications in the dental technology applications
  • For an international customer, the existing dentascope design had to be modified to allow synchronous measurements with 2 sensors, in order to achieve higher measuring speed
  • The work included integration of a new 1M-Pixel image sensor (IBIS5) in the design and the implementation of the synchronicity between two arbitrary sensors for parallel measurements
  • Design coordinator and system architect
  • Shared responsibility for Hardware- and software development and integration and PCB designing

C++ VHDL Altera Quartus Altium Designer Nios Ethernet TCP/IP I2C Analog Electronics Logic Analyzer Oscilloscope MS Project
Hightronix GmbH
6 Monate
2004-01 - 2004-06

Prototype 3D-Scanner with embedded TCP/IP Interface

System and Hardware Development Engineer C++ VHDL Altera Quartus ...
System and Hardware Development Engineer

  • The existing measuring head, which had most of its electronics placed on an ISA-Bus based card, had to be decoupled from the host computer and the whole electronics had be placed in the measuring head itself and the communication between the measuring head and the host computer had to be realized by TCP/IP interface
  • Here I had the opportunity to architecture a whole new system
  • Lead-Designer and system architect
  • I developed the system on the basis of Altera's softcore processor NIOS. As embedded TCP/IP-solution I decided to take a hard-wired TCP/IP
  • As a prototype I developed the whole design as a piggy-back PCB on Altera's Apex evaluation board

C++ VHDL Altera Quartus Altera SOPC Nios Ethernet TCP/IP Analog Electronics Logic Analyzer Oscilloscope several other lab instruments
Hightronix GmbH
3 Monate
2003-10 - 2003-12

SDH/SONET Network Processor

ASIC Design Engineer Astro RC-Extract Assura ...
ASIC Design Engineer

  • This ASIC component was designed by Munich Design-Center team on behalf of a renowned international customer
  • The design was very timing critical, since this component supports bit-rates of 2.5G and 10G
  • This chip was to be fabricated with 130 nm process
  • Worked on timing closure of some parts of the design
  • I integrated SERDES macro (Serializer/Deserializer) in the design and I generated test-vectors in order to test SERDES and PRBS macros

Astro RC-Extract Assura Prime Time NC-Verilog Formality TCL Perl
Agere Systems
2 Jahre 9 Monate
2001-04 - 2003-12

Back-End designing

ASIC Design Engineer
ASIC Design Engineer

  • Formerly Lucent-Microelectronics, Agere Systems mostly supplied telecommunication ASICs for back-bone networks
  • I worked mainly in Back-End designing (Timing-driven Layout, Floor-Planning, Static Timing Analysis, Design for Testability, functional and timing simulations)

Agere System, Munich-Design-Center
1 Jahr 4 Monate
2002-06 - 2003-09

SDH/SONET Network Termination Device (TADM2)

ASIC Design Engineer Design Compiler NC-Verilog Formality ...
ASIC Design Engineer

  • TADM2 was a redesign of Agere System's TADM chip, which realizes a highly integrated Network termination device for ring and linear networks with flexible payload mapping
  • Bad test coverage was one of the main reasons for the redesign of TADM
  • I worked on the improvement of test coverage
  • One of the reasons of the bad test coverage were unfixed hold-time violations, which were corrected by the colleagues by introducing lock-up latches
  • With this improved design and by using newest ATPG algorithms I could significantly improve the test coverage of the device

Design Compiler NC-Verilog Formality TCL Perl Tetramax
Agere Systems
1 Jahr
2001-06 - 2002-05

PDH-Mapper ASIC

ASIC Design Engineer Jupiter NC-Verilog Formality ...
ASIC Design Engineer

  • This mapper ASIC was designed on behalf of a big international concern
  • The component can process 24 STS-1 or DS3 channels in parallel
  • Die circuit was realized with 0.16 ?m process
  • Worked on timing closure of some high frequency blocks of the design
  • Further I defined pin out of the device on the basis of the toplevel-floorplan and conducted package verification using OPUS/NEXUS tools
  • Worked closely with test engineer and provided test vectors

Jupiter NC-Verilog Formality Ikos HSPICE OPUS Nexus Perl Scripting
Agere Systems
1 Jahr
2001-06 - 2002-05

Line-ASIC

ASIC Design Engineer Design Compiler Verilog NC-Verilog ...
ASIC Design Engineer

  • Line-ASIC project was canceled by the customers
  • Following tasks were accomplished by me in the Quotation phase
  • Programming of a Verilog test-bench for a parameterized dual-clock FIFO
  • from the Synopsys Design-Ware Components
  • Due to the big bit width requirement, the FIFO was realized by a combination of two FIFOs of half bit width

Design Compiler Verilog NC-Verilog Synopsys DesignWare
Agere Systems

Aus- und Weiterbildung

Aus- und Weiterbildung

2 Jahre 1 Monat
2016-09 - 2018-09

Certified Tester Foudation Level

Certified Tester Foudation Level, ISTQB
Certified Tester Foudation Level
ISTQB

Kompetenzen

Kompetenzen

Top-Skills

FPGA design, Software development, ASIC-Design Test Engineering

Produkte / Standards / Erfahrungen / Methoden

Altera Quartus
Altera SOPC
Altium Designer
Amazon AWS
Apollo
Assura
Astro
CVS
Debussy
Design Compiler
Django
Eclipse
Formality
GCC
IoT-Device
JBuilder
ModelSim
MS Office
MS Project
MS Visual Studio
NC-Verilog
Nexus
OAuth 2.0
ObjectAda
Oscilloscope
Prime Time
Protel
Questa Sim
Requirements Engineering
RTL Compiler
SoC Encounter
Spyglass
Subversion
Tetramax

Summary:

  • 23 years of experience in development, test and verification of Embedded Systems
  • Extensive experience in development and verification of digital systems (ASICs and FPGAs)
  • Expert knowledge in programming in C++ and C in embedded and application programming
  • Hands-on experience in all phases of product development, from concept to implementation, testing and application.
  • Agile software development in a scrum team. Experience in OOA/OOD, Requirements Engineering and Testing.
  • Experience with inter-chip and intra-chip communications standards and bus systems like Avalon, AMBA (AHB, APB, AXI), SPI, I2C.
  • Experience with microprocessor cores like NIOS, ARM Cortex-A9, TriCore, Xtensa, PIC.
  • Bring-up experience of complex embedded systems.
  • Branches experience: automotive, telecommunication, aerospace and software houses.


Libraries:

  • OWL
  • STL
  • QT


Digital Design Tools:

  • Quartus
  • Libero
  • ISE
  • Vivado
  • Questa
  • ModelSim
  • Design Compiler
  • RTL-Compiler
  • SoC Encounter
  • Apollo
  • Prime Time
  • Formality
  • NC-Verilog
  • Tetramax
  • HSPICE
  • Gnu-Make
  • Altium Designer
  • Eagle


Compilers and IDEs:

  • gcc
  • Eclipse
  • Microsoft Visual Studio
  • gnu-Make
  • JBuilder
  • ObjectAda


Debuggers:

  • gdb
  • Universal Debug Engine (UDE)


RTOS:

  • linux, µC/OS-II, eCos, Android


Lab Instruments:

  • Hands-on experience with lab instruments like oscilloscopes, logic analyzers, signal generators


Version-Control -Software:

  • Subversion (svn)
  • Microsoft TFS
  • Git
  • Microsoft Office


Student work and Internships:

03/2000 - 03/2001

Student employee at the Chair of process and aerosol measurement technology, University of Duisburg-Essen. I worked on the development of a CAN-Bus Network of measurement nodes for the synchronous measurements. I did my master?s thesis in the same institute on the topic "CAN-Network of peripheral sensors of an optical particle counter?. For the development I used CAN-Controller of Microchip and PIC microcontroller.


12/1998 - 06/1999

Worked with Infineon Technologies development center in Düsseldorf and programmed a driver software for the Infineon component FALC56 .


10/1998 - 06/1999

GUI-programming of a driving dynamics simulator with Java and CORBA at the Institute of Mechatronics at the University of Duisburg-Essen.


09/1998 - 11/1998

Worked with Infineon Technologies, development center Düsseldorf and developed a testbench in VHDL to the test the Line-Interface of the Infineon component FALC. The work included behavioral description of different line coders and decoders.


06/1997 - 04/1998

Worked as a student employee at the Chair of Automation Technology at Ruhr-University Bochum. I worked as a C++ Programmer on the development of an image processing system for contactless geometry acquisition.

Betriebssysteme

eCos
Linux
Windows
?Clinux

Programmiersprachen

Ada
C
C++
C/C++
Java
JavaScript
Perl
Python
SCPI
Scripting
TCL
VHDL
Verilog
SystemC
Ada95

Datenkommunikation

AXI-Lite
AXI4-Stream
CAN-Bus
Ethernet
Gigabit Ethernet
I2C
SPI
TCP/IP

Hardware

ASIC
DSP
FPGA design
Lab Equipment
Nios
SystemC
Verilog
VHDL

Berechnung / Simulation / Versuch / Validierung

HSPICE
MATLAB
ModelSim
NC-Sim

Design / Entwicklung / Konstruktion

OOA / OOD / OOP
Scrum
UML
XILINX Vivado

Branchen

Branchen

  • Halbleiter
  • Telekommunikation
  • Industrie
  • EDA(Electronic Design Automation)
  • Automotiv

Einsatzorte

Einsatzorte

Deutschland, Österreich, Schweiz

Großbritannien

nicht möglich

Projekte

Projekte

10 Monate
2023-06 - heute

Design and Simulation of an SDR-System

Consultant FPGA Development
Consultant FPGA Development
VHDL Xilinx UltraScale+ Zynq FPGA Vivado Riviera Pro Vunit
1 Jahr 9 Monate
2022-07 - heute

FPGA development

Consultant DSP and FPGA Development
Consultant DSP and FPGA Development
  • Worked on FPGA development of a highly innovative hand-held radar for weapons search
  • Hardware/Software distribution
  • Implementation of parts of DSP in FPGA
Verilog Xilinx UltraScale+ Zynq FPGA Vivado Modelsim MATLAB
Lassen Peak Inc.
4 Monate
2023-01 - 2023-04

Feasibility study for an image processing solution

FPGA-Design Engineer
FPGA-Design Engineer

  • Worked on feasibility study for an image processing solution
  • Evaluated different possibilities for the solution
  • Devised several solutions and simulated them in python to select an optimal one
  • Realized the same in VHDL 

VHDL Xilinx UltraScale+ Zynq FPGA Vivado Python
Alltec Laser/FOBA Laser
3 Jahre 10 Monate
2018-09 - 2022-06

FPGA development of an award-winning hand-held LIDAR

Consultant FPGA Development and Test
Consultant FPGA Development and Test

  • Worked on FPGA development of an award-winning hand-held LIDAR based 3D-Scanning system
  • Integrated Image sensors and other peripherals in the system
  • Realized a part of imaging pipeline in FPGA
  • Also developed a python test suit for the system level tests

VHDL Microsemi Polarfire FPGA Libero 12.1 Modelsim Python QT5 Linux C
Leica Geosystems AG
1 Jahr 7 Monate
2017-02 - 2018-08

?Space? department on development of a Solar Array Simulator

Consultant Hardware/Software Development VHDL ModelSim JavaScript ...
Consultant Hardware/Software Development

  • Worked in the ?Space? department on development of a Solar Array Simulator, used in verification and test of Satellite?s power system

VHDL ModelSim JavaScript SCPI Lab Equipment scrum XILIX ISE Modelsim Altium Designer Python
Siemens CVC GmbH
Wien
4 Monate
2017-03 - 2017-06

Development of a Gigabit-Ethernet Switch

Consultant in FPGA-Development Gigabit Ethernet AXI4-Stream AXI-Lite ...
Consultant in FPGA-Development

  • Worked on the development of a Gigabit Ethernet Switch as a part of a new concept of next generation high speed servers
  • It was used as a packet switch between a 40 Gb Ethernet on one side and 6 microprocessor cores, each connected with a 10 Gb Ethernet on the other side

Gigabit Ethernet AXI4-Stream AXI-Lite VHDL Python XILINX Vivado Questa Sim Xilinx Vivado Questa AMBA AXI4-Stream
Hybridserver Tec GmbH
Norderstedt
3 Monate
2016-11 - 2017-01

Embedded Software and "Skills" development for IoT and Cloud Applications

Consultant for Embedded Software Development for IoT Python ?Clinux Requirements Engineering ...
Consultant for Embedded Software Development for IoT

  • Worked on further development of their product WiButler
  • Worked on smart-home ?skill? development for Amazon-Echo

Python ?Clinux Requirements Engineering Django OAuth 2.0 Amazon AWS IoT-Device scrum JavaScript
IExergy GmbH
3 Jahre 1 Monat
2013-09 - 2016-09

Test and validation of a new generation of inverters

R&D Consultant for Verification and Validation
R&D Consultant for Verification and Validation

  • Worked on test and validation of a new generation of inverters (frequency converters). Inspected all its existing requirements for sanity and redundancy. Wrote requirements for ?undefined? parts of the system keeping international norms (like IEC 61131) in consideration. Suggested tests for those requirements. Carried them out and documented each test.
  • Worked specifically on ?encoder signal processing? and binary inputs/outputs by writing requirements, suggesting tests for those requirements and carrying out and documenting those tests during and after the development.
  • Developed and verified an SPI-based ?diagnosis interface? (using VHDL) for inverters to get and display the key parameters of inverter during its operation.
  • Introduced regression tests for hardware-software system testing. Developed a scripting framework for regression tests based on UDEDebugger?s COM interface, Quartus tcl interface, Perl scripting and Make files.
  • Introduced IP-XACT (metadata) based system design and documentation flow. Evaluated different off-the-shelf IPXACT tools on behalf of SEW but the developers were not happy with their end results. I ended up writing my own tool using extensive Python scripting. Both hardware and firmware development teams have readily accepted it. This tool takes IP-XACT description as input and generates Hardware Abstraction Layer (HAL) in C++, Register Interfaces in VHDL and html documentation of all memory mapped register. This tool has eliminated a major cause of faults in the design flow.
  • Worked on a system-tester based on a Cyclone-V board with Cortex-A9 cores and ?Clinux. Tested the board by writing simple drivers. Developed a web-service (SOAP) based interface between PC and the test board. 

Python C++ RE VHDL Quartus Modelsim ?Clinux Cyclone-V Arm Cortex-A9 IP-XACT oscilloscope logic analyzer TriCore UDE-Debugger COM SOAP
SEW Eurodrive GmbH & Co. KG
1 Jahr 1 Monat
2012-06 - 2013-06

Design, development and verification of a new field bus

R&D Consultant C C++ NIOS ...
R&D Consultant

  • Design, development and verification of a new field bus
  • The design was implemented on an FPGA development board
  • My responsibilities included development and verification of Layer 2 and 3 of the devised communication protocol of this new Ethernet-compatible field-bus

C C++ NIOS Perl DSP Lab instruments like oscilloscope and logic analyzer
Robert Bosch GmbH (Corporate Research)
1 Jahr 5 Monate
2011-01 - 2012-05

Digital IC Design

Consultant VHDL ModelSim Spyglass ...
Consultant

  • As a part of the IC-Design team I was involved in design and verification of  several LTE-Baseband chips
  • My activities involved RTL-coding for a given DSP algorithm, functional verification, linting and trial synthesis

VHDL ModelSim Spyglass Design Compiler AMBA Tensilica DSP FFT C
Intel Mobile Communications Dresden GmbH
2 Jahre 9 Monate
2008-05 - 2011-01

Processed the customers? C++/SystemC code

Corporate Application Engineer
Corporate Application Engineer

  • As a Corporate Application Engineer at ChipVision Design Systems, I had the responsibility to serve as an interface between customers and engineering team
  • As a part of my responsibility, I processed the customers? C++/SystemC code to perform high-level-synthesis with PowerOpt and verified the correctness of the generated RTL-Verilog by simulation

ChipVision Design Systems AG
5 Jahre 7 Monate
2005-07 - 2011-01

Software Developement

Corporate Application Engineer/ Senior Software Developer
Corporate Application Engineer/ Senior Software Developer

  • ChipVision Design Systems is an EDA(Electronic Design Automation) company, which has specialized in low-power high-level-synthesis
  • As Senior Software Developer I contributed towards development of this future oriented technology and as Corporate Application Engineer I contributed towards effective application of this technology by the customers

ChipVision Design Systems AG
1 Jahr
2007-05 - 2008-04

Programming of a Verilog-Writers

Senior Software Development Engineer C++ Verilog Icarus ...
Senior Software Development Engineer

  • ChipVision's high-level-synthesis tool PowerOpt outputs the RTL in Verilog
  • Special attention is given on the readability of the generated code
  • As a part of my work in the back-end group, I explored the forms of expression in Verilog, which express the structure of the generated circuit in a more readable fashion
  • Worked in a Scrum team to realize the Verilog-Writer

C++ Verilog Icarus Cadence RTL-Compiler Eclipse Scrum
ChipVision Design Systems AG
4 Monate
2007-01 - 2007-04

Requirements gathering for PowerOpt

EDA Development Engineer
EDA Development Engineer

  • ChipVision decided to bring out a high-level-synthesis tool in the beginning of 2007
  • Requirements gathering was obviously the the first step in the huge project ahead
  • At that phase, I interacted with two groups: Synthesis Kernel Group and Back-End-Group
  • I took part in brain storming sessions to capture the requirements for the new Product PowerOpt

ChipVision Design Systems AG
1 Jahr 6 Monate
2005-07 - 2006-12

LEMOS - Low-Power Design Methods for Mobile Systems

EDA Development Engineer Verilog C++ Qt Libaries ...
EDA Development Engineer

  • Mobile systems have special requirements on low power design methods
  • In this project, new methods for estimation and optimization of dissipation losses in the mobile systems were explored
  • As a part of this research project, I analyzed clock trees, which are highly critical networks with respect to dissipation losses
  • As a result of this research, new methods for estimation and optimization of dissipation losses were developed
  • I verified the developed models using Cadence's SoC Encounter
  • I integrated the source-code in ChipVision's estimation tool ORINOCO

Verilog C++ Qt Libaries SoC Encounter NC-Sim X-Graph Eclipse
ChipVision Design Systems AG
11 Monate
2004-08 - 2005-06

OSIS Compliant Measuring Head

System and Hardware Development Engineer C++ VHDL Altera Quartus ...
System and Hardware Development Engineer

  • OSIS is an emerging standard for the electromechanical and software interfaces of the measuring heads for coordinate measurement machines (CMMs)
  • The goal of the project was to integrate a higher resolution image sensor (LUPA4000) in the design and thereby considering all compliance guidelines from OSIS consortium
  • Digital high speed hardware (FPGA based) and embedded software development, PCB-Design and layout, System Integration and testing

C++ VHDL Altera Quartus Protel Analog Electronics MS Project
Hightronix GmbH
1 Jahr 6 Monate
2004-01 - 2005-06

Hardware Development Engineering

System and Hardware Development Engineer
System and Hardware Development Engineer

  • Worked on development of highly precise laser based 3D optical sensors for coordinate measurement machines
  • As a System and Hardware Development Engineer, I developed the concepts, realized them in Hardware and Software and tested and debugged the products until their production maturity

Hightronix GmbH
10 Monate
2004-06 - 2005-03

Dentascope with 2 synchronous optical 3D-Sensors

System and Hardware Development Engineer C++ VHDL Altera Quartus ...
System and Hardware Development Engineer

  • Dentascope was a compact and highly precise 3D Scanner, especially designed for applications in the dental technology applications
  • For an international customer, the existing dentascope design had to be modified to allow synchronous measurements with 2 sensors, in order to achieve higher measuring speed
  • The work included integration of a new 1M-Pixel image sensor (IBIS5) in the design and the implementation of the synchronicity between two arbitrary sensors for parallel measurements
  • Design coordinator and system architect
  • Shared responsibility for Hardware- and software development and integration and PCB designing

C++ VHDL Altera Quartus Altium Designer Nios Ethernet TCP/IP I2C Analog Electronics Logic Analyzer Oscilloscope MS Project
Hightronix GmbH
6 Monate
2004-01 - 2004-06

Prototype 3D-Scanner with embedded TCP/IP Interface

System and Hardware Development Engineer C++ VHDL Altera Quartus ...
System and Hardware Development Engineer

  • The existing measuring head, which had most of its electronics placed on an ISA-Bus based card, had to be decoupled from the host computer and the whole electronics had be placed in the measuring head itself and the communication between the measuring head and the host computer had to be realized by TCP/IP interface
  • Here I had the opportunity to architecture a whole new system
  • Lead-Designer and system architect
  • I developed the system on the basis of Altera's softcore processor NIOS. As embedded TCP/IP-solution I decided to take a hard-wired TCP/IP
  • As a prototype I developed the whole design as a piggy-back PCB on Altera's Apex evaluation board

C++ VHDL Altera Quartus Altera SOPC Nios Ethernet TCP/IP Analog Electronics Logic Analyzer Oscilloscope several other lab instruments
Hightronix GmbH
3 Monate
2003-10 - 2003-12

SDH/SONET Network Processor

ASIC Design Engineer Astro RC-Extract Assura ...
ASIC Design Engineer

  • This ASIC component was designed by Munich Design-Center team on behalf of a renowned international customer
  • The design was very timing critical, since this component supports bit-rates of 2.5G and 10G
  • This chip was to be fabricated with 130 nm process
  • Worked on timing closure of some parts of the design
  • I integrated SERDES macro (Serializer/Deserializer) in the design and I generated test-vectors in order to test SERDES and PRBS macros

Astro RC-Extract Assura Prime Time NC-Verilog Formality TCL Perl
Agere Systems
2 Jahre 9 Monate
2001-04 - 2003-12

Back-End designing

ASIC Design Engineer
ASIC Design Engineer

  • Formerly Lucent-Microelectronics, Agere Systems mostly supplied telecommunication ASICs for back-bone networks
  • I worked mainly in Back-End designing (Timing-driven Layout, Floor-Planning, Static Timing Analysis, Design for Testability, functional and timing simulations)

Agere System, Munich-Design-Center
1 Jahr 4 Monate
2002-06 - 2003-09

SDH/SONET Network Termination Device (TADM2)

ASIC Design Engineer Design Compiler NC-Verilog Formality ...
ASIC Design Engineer

  • TADM2 was a redesign of Agere System's TADM chip, which realizes a highly integrated Network termination device for ring and linear networks with flexible payload mapping
  • Bad test coverage was one of the main reasons for the redesign of TADM
  • I worked on the improvement of test coverage
  • One of the reasons of the bad test coverage were unfixed hold-time violations, which were corrected by the colleagues by introducing lock-up latches
  • With this improved design and by using newest ATPG algorithms I could significantly improve the test coverage of the device

Design Compiler NC-Verilog Formality TCL Perl Tetramax
Agere Systems
1 Jahr
2001-06 - 2002-05

PDH-Mapper ASIC

ASIC Design Engineer Jupiter NC-Verilog Formality ...
ASIC Design Engineer

  • This mapper ASIC was designed on behalf of a big international concern
  • The component can process 24 STS-1 or DS3 channels in parallel
  • Die circuit was realized with 0.16 ?m process
  • Worked on timing closure of some high frequency blocks of the design
  • Further I defined pin out of the device on the basis of the toplevel-floorplan and conducted package verification using OPUS/NEXUS tools
  • Worked closely with test engineer and provided test vectors

Jupiter NC-Verilog Formality Ikos HSPICE OPUS Nexus Perl Scripting
Agere Systems
1 Jahr
2001-06 - 2002-05

Line-ASIC

ASIC Design Engineer Design Compiler Verilog NC-Verilog ...
ASIC Design Engineer

  • Line-ASIC project was canceled by the customers
  • Following tasks were accomplished by me in the Quotation phase
  • Programming of a Verilog test-bench for a parameterized dual-clock FIFO
  • from the Synopsys Design-Ware Components
  • Due to the big bit width requirement, the FIFO was realized by a combination of two FIFOs of half bit width

Design Compiler Verilog NC-Verilog Synopsys DesignWare
Agere Systems

Aus- und Weiterbildung

Aus- und Weiterbildung

2 Jahre 1 Monat
2016-09 - 2018-09

Certified Tester Foudation Level

Certified Tester Foudation Level, ISTQB
Certified Tester Foudation Level
ISTQB

Kompetenzen

Kompetenzen

Top-Skills

FPGA design, Software development, ASIC-Design Test Engineering

Produkte / Standards / Erfahrungen / Methoden

Altera Quartus
Altera SOPC
Altium Designer
Amazon AWS
Apollo
Assura
Astro
CVS
Debussy
Design Compiler
Django
Eclipse
Formality
GCC
IoT-Device
JBuilder
ModelSim
MS Office
MS Project
MS Visual Studio
NC-Verilog
Nexus
OAuth 2.0
ObjectAda
Oscilloscope
Prime Time
Protel
Questa Sim
Requirements Engineering
RTL Compiler
SoC Encounter
Spyglass
Subversion
Tetramax

Summary:

  • 23 years of experience in development, test and verification of Embedded Systems
  • Extensive experience in development and verification of digital systems (ASICs and FPGAs)
  • Expert knowledge in programming in C++ and C in embedded and application programming
  • Hands-on experience in all phases of product development, from concept to implementation, testing and application.
  • Agile software development in a scrum team. Experience in OOA/OOD, Requirements Engineering and Testing.
  • Experience with inter-chip and intra-chip communications standards and bus systems like Avalon, AMBA (AHB, APB, AXI), SPI, I2C.
  • Experience with microprocessor cores like NIOS, ARM Cortex-A9, TriCore, Xtensa, PIC.
  • Bring-up experience of complex embedded systems.
  • Branches experience: automotive, telecommunication, aerospace and software houses.


Libraries:

  • OWL
  • STL
  • QT


Digital Design Tools:

  • Quartus
  • Libero
  • ISE
  • Vivado
  • Questa
  • ModelSim
  • Design Compiler
  • RTL-Compiler
  • SoC Encounter
  • Apollo
  • Prime Time
  • Formality
  • NC-Verilog
  • Tetramax
  • HSPICE
  • Gnu-Make
  • Altium Designer
  • Eagle


Compilers and IDEs:

  • gcc
  • Eclipse
  • Microsoft Visual Studio
  • gnu-Make
  • JBuilder
  • ObjectAda


Debuggers:

  • gdb
  • Universal Debug Engine (UDE)


RTOS:

  • linux, µC/OS-II, eCos, Android


Lab Instruments:

  • Hands-on experience with lab instruments like oscilloscopes, logic analyzers, signal generators


Version-Control -Software:

  • Subversion (svn)
  • Microsoft TFS
  • Git
  • Microsoft Office


Student work and Internships:

03/2000 - 03/2001

Student employee at the Chair of process and aerosol measurement technology, University of Duisburg-Essen. I worked on the development of a CAN-Bus Network of measurement nodes for the synchronous measurements. I did my master?s thesis in the same institute on the topic "CAN-Network of peripheral sensors of an optical particle counter?. For the development I used CAN-Controller of Microchip and PIC microcontroller.


12/1998 - 06/1999

Worked with Infineon Technologies development center in Düsseldorf and programmed a driver software for the Infineon component FALC56 .


10/1998 - 06/1999

GUI-programming of a driving dynamics simulator with Java and CORBA at the Institute of Mechatronics at the University of Duisburg-Essen.


09/1998 - 11/1998

Worked with Infineon Technologies, development center Düsseldorf and developed a testbench in VHDL to the test the Line-Interface of the Infineon component FALC. The work included behavioral description of different line coders and decoders.


06/1997 - 04/1998

Worked as a student employee at the Chair of Automation Technology at Ruhr-University Bochum. I worked as a C++ Programmer on the development of an image processing system for contactless geometry acquisition.

Betriebssysteme

eCos
Linux
Windows
?Clinux

Programmiersprachen

Ada
C
C++
C/C++
Java
JavaScript
Perl
Python
SCPI
Scripting
TCL
VHDL
Verilog
SystemC
Ada95

Datenkommunikation

AXI-Lite
AXI4-Stream
CAN-Bus
Ethernet
Gigabit Ethernet
I2C
SPI
TCP/IP

Hardware

ASIC
DSP
FPGA design
Lab Equipment
Nios
SystemC
Verilog
VHDL

Berechnung / Simulation / Versuch / Validierung

HSPICE
MATLAB
ModelSim
NC-Sim

Design / Entwicklung / Konstruktion

OOA / OOD / OOP
Scrum
UML
XILINX Vivado

Branchen

Branchen

  • Halbleiter
  • Telekommunikation
  • Industrie
  • EDA(Electronic Design Automation)
  • Automotiv

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