I prefer a broad scope of activities.
I take responsibility for digital design projects starting from requirements engineering, project planning, system architecture, digital implementation, verification, and validation.
System architecture
Algorithm optimization
ASIC: Standard cell circuits
CPUs: ARM Cortex, RISC-V, TI C2000, Xilinx Microblaze, custom instruction set
Elliptic Curve Cryptography
Ethernet 1G 10G
Gigabit AES encryption
Signal processing
Xilinx / Intel / Efinix FPGA
Windows, Linux
Verilog 2001, Systemverilog, TCL,
Java, Python, C++, ANSI C
Ethernet: 1G, 10G, MDIO, SFP, SFP+
I2C, SPI, I2S, SPDIF
Linux-Server
Windows Notebook
Elektronik-Labor (Oszilloskop, Lötstation, ...)
Xilinx FPGA-Boards
Microcontroller Evaluation Boards
8x 1G -> 1x 10G network concentrator (FPGA based; own development)
Model-based design
Mentor, Cadence, Xilinx
Regression tests (TCL, HDL testbench)
Post layout simulation (SDF annotation)
Hardware Konzeption
Hardware Entwicklung
Signalverarbeitung
Security
Verifikation
I prefer to take over high-level challenges. And turn them in a top-down approach into a highly-optimized solution which can be verified.
Halbleiterindustrie, Universitäten und ausseruniversitäre Forschung
I prefer a broad scope of activities.
I take responsibility for digital design projects starting from requirements engineering, project planning, system architecture, digital implementation, verification, and validation.
System architecture
Algorithm optimization
ASIC: Standard cell circuits
CPUs: ARM Cortex, RISC-V, TI C2000, Xilinx Microblaze, custom instruction set
Elliptic Curve Cryptography
Ethernet 1G 10G
Gigabit AES encryption
Signal processing
Xilinx / Intel / Efinix FPGA
Windows, Linux
Verilog 2001, Systemverilog, TCL,
Java, Python, C++, ANSI C
Ethernet: 1G, 10G, MDIO, SFP, SFP+
I2C, SPI, I2S, SPDIF
Linux-Server
Windows Notebook
Elektronik-Labor (Oszilloskop, Lötstation, ...)
Xilinx FPGA-Boards
Microcontroller Evaluation Boards
8x 1G -> 1x 10G network concentrator (FPGA based; own development)
Model-based design
Mentor, Cadence, Xilinx
Regression tests (TCL, HDL testbench)
Post layout simulation (SDF annotation)
Hardware Konzeption
Hardware Entwicklung
Signalverarbeitung
Security
Verifikation
I prefer to take over high-level challenges. And turn them in a top-down approach into a highly-optimized solution which can be verified.
Halbleiterindustrie, Universitäten und ausseruniversitäre Forschung