• Execute tape-out activities and prepare photomask data for production (a write-ready mask), including frame generation, multi-die placement, capturing, and resolution enhancement techniques within scribe street
• Leverage Mask Compose using Cadence Pegasus; creating alignment/overlay markers, metrology targets, EM structure, CD control, process/defect monitoring cells using TSMC and TI processes, Mask data release.
• Conduct Optical Proximity Correction, Lithography to improve yield at the 300 mm wafer fab; Programm-ing scripts to streamline the design-to-mask workflow.

• Specialize in Calibre IC Physical implementation, ensuring efficient design verification and Design for Manufacturing (DFM) optimization for faster production and complete sign-off compliance. -Providing on-site and online EU customer?s support.
• Develop and debug customer software, address tool enhancement requests, collaborate closely with R&D. -Improve user experience by integrating feedback into application design and functionality for advanced nanometer silicon chip development.
• Conduct code reviews and debugging, driving best practices and enhancing overall code quality for customer PDK (Process Desing Kit) teams.
• Deliver training sessions on Programmable Electrical Rules Checking (PERC) and DFM Smart-FILL/ECO-FILL.
• Expertise in PERC, ESD/LUP, DFM methodologies, Photonics devices DRC (non-rectangle, curvilinear).
• Proficient in coding, debugging in the programming. -Familiar with advanced technologies across multiple foundries, LVS, ERC, Antenna, Parasitic Extraction, xACT, DESIGNrev, Interactive and TCL/TK scripts. -License agreements, NDAs, tracking on Salesforce.

Graphics -Dedicated to IC Manufacturing Backend, Customer Application Engineering for Calibre RET/OPC (Optical Proximity Correction)

• Expertise in Resolution Enhancement Technology(RET) and Mask Data Preparation (MDP) for Foundries.
• Skilled in OPC simulation (ILT) and OPC-VERIFY.
• Experienced with Sub-Resolution Assist Feature(SRAF), ModelFlow, Multi-Patterning, LithoView, Workbench, MPC (mask process correction) and Jobdeck. -Developed manufacturable layouts for process development and yield improvement.
• Optimize flows to enhance wafer pattern fidelity. -Lithography engineering with GlobalFoundries, ST- Microelectronics, Infineon and Intel in Europe. -On-site and online customer support.

• Consulted as a Sales Engineer to develop the automotive ADAS (Advanced Driver Assistance) market.
• Managed customer development in China and Korea.
• Specialized in Digital Signal Processors with multi-camera, software/hardware, Ethernet, LVDS, surround-view, and traffic sign recognition technologies.
• Developed Asian customers including Delphi, Desay AV Auto, Hyundai-Mobis and Mando.

• Wrote chip Packaging design rules using Siemens Calibre for Wire-bond BGA, TSSOP and L-/T-/MQFP.
• Defined and released package DRC, created test cases, and qualified package designs.
• Acted as the interface between chip package product offerings and OSAT partners Amkor, ASE Technology.

• Managed distributors and regional sales operations, including customer ASIC development projects.
• Acted as the sales representative between head-quarter and the Asia-Pacific region, ensuring alignment on strategy and execution.
• Secured key accounts and led successful annual price negotiations, maintaining and growing revenue stream.
• Collaborated cross-functionally with Marketing, Design, Product, QA, Logistics, and Finance teams to deliver customer solutions.
• Conducted market and competitive analysis, providing regular sales forecasts and reports to management.
• Delivered technical sales support, negotiated and closed agreements including NDAs, BPAs, and MOUs.
• Managed strategic customer relationships with Asian automative companies: Hyundai-Mobis, Sanyo, Visteon, Alpine, ALPS, Panasonic, Mitsubishi, Fuji Electric, Continental, Delphi, Desay AV Auto, and Mando.
• Drove sales of semiconductor IC products including 3D gesture control sensors, Ultrasonic parking sensors (?15M revenue in 2012), power supplies, IGBT drivers, pressure sensors, motor driver, FlexRay, CAN/LIN SBC.

• Led physical design team, Wrote Hercules DRC/LVS rules, optimizing Dracula and Assura LVS/DRC. 
• Mask revision for 256Mb Low Power SDRAM.

• Designed and simulated core and peripheral Circuits, including decoders, PLL, I/O drivers, ESD/LUP, sense amplifiers, Refresh, State machine, voltage regulators, and low-power generators in 256MB and 512MBDDR1.
• Directed chip-level architecture, specification, and floor planning, ensuring functional correctness and timing closure, and measuring and testing on silicon.
• Executed static timing analysis, failure analysis, and silicon testing, improving performance and reliability.
• Optimized Clock distribution, Power integrity, and ADC/DAC design for high-speed memory systems.
• Defined and verified DDR1 DRAM specifications, completed functional verification, and conducted large-scale post-simulation using HSPICE and HSIM.
• Coordinated the Physical Design team, floor plan in a chip, overseeing tape-outs, sign-off processes, mask data preparation, RC extraction, Dummy fill generation, completed multiple mask revisions in memory devices.
• Performed full-chip physical IC design for SDRAM and DDR1 cores and peripheral parts with expertise in Analog and mixed-signal layout at low voltages.
• Led automation flow development, creating Cadence SKILL programs for Place & Route (P&R, RTL-to-GDS) and validating flows with Synopsys IC Compiler.
• Wrote DRC/LVS rule decks using Mentor Calibre, Synopsys Hercules, and Cadence Assura.
• Received the Excellence in Innovation Award for contributions to design methodology and automation.