PROFESSIONAL PROFILE

Engineering manager with 25+ years of end-to-end semiconductor product experience?from RTL design to product end-of-life closure. Combines deep microelectronics expertise in automotive SoCs, AI ASICs, and high-security ChipCard controllers with proven leadership of large, geographically distributed engineering teams (50+ engineers). Trusted by Tier-1 names, including Infineon Technologies and AMS-OSRAM, to define methodology, drive industrial compliance, manage complex multi-derivative products, and ensure delivery on schedule. Operates as an independent B2B project management consultant, technical coach, and senior project manager to semiconductor organizations across Europe.

CORE COMPETENCIES

• Project & Portfolio Management
• Automotive Semiconductors (ISO 26262)
• Common Criteria Cybersecurity HW (EAL6+)
• AI / NASP ASIC Product Management
• Pre- and post-silicon product lifecycle management
• SoC Architecture & Digital Design
• IPMA / Agile / Stage-Gate Methodologies
• Configuration & Change Management
• Risk & Stakeholder Management
• Cross-functional Team Leadership (50+)
• Multi-site & International Team Coordination
• Tools: Jira, Confluence, MS Project, KLUSA, Synopsys

Work and Leadership Experience

2021 - today

Role: Senior Project Manager

Customer: Self-Employed, Munich, Germany

Tasks:

Project Management Consultant / Development Advisor ? POLYN Technology (UK / Germany)

Analog AI-enabled ASICs: automotive vibration control & voice-processing product lines

• Led full project management across two NASP ASIC products, aligning delivery with customer milestones and stakeholders? reporting cycles.
• Architected and deployed an advanced project management methodology, reducing planning overhead and improving on-time milestone achievement according to ISO 21500.
• Orchestrated the deployment of the advanced gate decision points and project phases ? successfully enabled the first standardized tape-out.
• Defined an ISO 26262-compliant result-driven development flow and implemented it for a pilot project to let the team learn and adhere to the requirements of functional safety.

Senior IP Project Manager ? Infineon Technologies AG (Germany)

AURIX 3G TC4X Family Microcontrollers

• Successfully managed concurrent development and release of Non-Volatile Memory subsystem, Computer/ADAS, Communication, and Cybersecurity IP subsystems for AURIX 3G TC4X ASIL-D automotive MCU family.
• Orchestrated development in 4 independent and geographically distributed teams.
• Led a cross-functional team of 50+ analog, digital, and firmware design engineers across multiple sites (UK, Germany, India), delivering IP functional blocks to plan within a complex program timeline.
• Drove change and configuration management processes, maintaining design integrity across multiple silicon revisions.

Project Manager ? AMS-OSRAM (Italy / Austria / Switzerland)

Automotive LED-control ASICs: portfolio of four concurrent projects

• Managed a portfolio of four automotive LED-driver ASIC projects, coordinating distributed teams across three countries, and serving different maturity stages of the products.
• Owned scoping, resource allocation, risk management, and customer releases for four product lines.
• Conducted pre- and post-silicon product development cycles between R&D and industrialization teams.

2015 - 2020

Role: Project Manager ? Product Certifications

Customer: Infineon Technologies AG, Munich, Germany

Tasks:

• Managed 30+ high-security SLx78XX/SLx90XX family MCU certifications (Common Criteria EAL6+, EMVCo, CUP) from project initiation through successful authority approval.
• Coordinated multi-disciplinary development teams, independent evaluation laboratories (Brightsight, TÜV, BSI, T-Systems, China FNRA/BCTC), and certification authorities, eliminating bottlenecks at key evaluation gates.
• Developed comprehensive certification project documentation and reported status to product management (Business Line and Technical Marketing Heads), enabling executive-level risk visibility.
• Planned and moderated IP subsystems design reviews and audits, ensuring security architecture compliance and accelerating evaluation cycles.

2006 - 2015

Role: Senior Staff Digital Design Engineer

Customer: Infineon Technologies Austria AG, Graz, Austria

Tasks:

• Architected clock and power management subsystems in high-security chipcard SLx78XX and SLx90XX MCU families ? products deployed in hundreds of millions of banking and government ID cards worldwide.
• Designed the multi-interface management and contactless power control subsystem, enabling ISO 14443 compliance.
• Supervised IP subsystems delivery and quality checks, top-level integration, regression, and configuration management for multiple product generations.
• Coordinated product sign-off reviews, release processes, and security certification activities, supporting EAL5+/EAL6+ evaluations.

2003 - 2006

Role: Technical Project Manager / Design Team Lead

Customer: SMC Videoscan, Moscow, Russia

Tasks:

• Designed the architecture and concept of ultra-fast video capture systems based on FPGA and custom PCB solutions.
• Led a digital design team through full development cycles (FPGA, microcontroller, PCB), delivering against budget and milestone commitments.
• Reported progress, budget, and resource status to executive stakeholders and supervised the product release and milestone closure process.

2000 - 2003

Role: Digital ASIC Designer

Customer: Nortel Networks, Ottawa, Canada

Tasks:

• Deployed bus functional models for OIF SPI-4.2, Utopia Level 3, and CSIX interfaces for the Q192 ASIC, a carrier-grade packet-processing device.
• Architected Synopsys VERA-HVL verification environments and behavioral models, and maintained functional regression at the module and system levels.
• Designed RTL for a proprietary high-speed ASIC-to-ASIC bus interface and authored technical documentation for the Q192 and OC48 queuing ASIC projects.

1997 - 2000

Role: Associate Professor, Computer Science Department

Customer: Vladimir State University, Russia

Tasks:

• Developed and delivered courses and lab sessions on digital design, FPGAs, and ASIC testing for undergraduate and postgraduate students.
• Supervised R&D projects and cooperation activities under the EUROCHIP / EUROPRACTICE framework, connecting academic research with industrial application.
• Planned and executed hands-on training courses on Xilinx/ALTERA FPGA design and verification for industry professionals.