Experienced Embedded Systems Architect. FPGA, Linux, Yocto.
Aktualisiert am 28.09.2023
Freiberufler / Selbstständiger
Verfügbar ab: 28.09.2023
Verfügbar zu: 100%
davon vor Ort: 20%
Video over IP
well in reading and understanding


Unterwasser (Schweiz) (+50km)
Deutschland, Schweiz, Österreich


2021 - 2023: Implemented Wireguard VPN protocol

Role: Principal Systems Architect

Customer: BrightAI B.V., Full Remote, Switzerland, The Netherlands


  • Implemented Wireguard VPN protocol in FPGA for 100 Gbit/s SmartNIC on AMD Alveo U50. Architect and lead small team, code implementation. Vivado SpinalHDL, SystemVerilog, C, Rust, VexRiscv, RISC-V, Verilator, GHDL, CocoTB, SpinalSim, CI/CD.

2008 - 2023: Helped approx. 70 high-tech companies

Role: Embedded Systems Consultant

Customer: on request, Eindhoven, The Netherlands


  • Helped approx. 70 high-tech companies. Define CPU, SoC, GPU, FPGA system architectures (COTS/custom hardware, RTL firmware, open-source, proprietary software), make trade-offs, select hardware components, open-source software, implement board support software, FPGA firmware, kernel ports, device drivers, middleware and applications.
  • I work remotely in own office and lab spaces, fixed price or on hourly tarif.

Developed own products portfolio

  • Come up with, design, develop, sell and provide intellectual property and support.
  • Lancero PCI Express SGDMA PCIe for Intel FPGA which is the background technology for Amazon AWS ECS F1 FPGA acceleration.
  • JPEG-LS Lossless image compressor for AMD/Intel FPGA?s,
  • i.MX53/Cyclone V industrial camera reference design.


  • Some of my direct customers include Cymer/USA, ASML/Netherlands
  • Robert Bosch Car Multimedia GmbH/Germany
  • Philips Innovation Services/Netherlands
  • National Institute of Standards and Technology/USA
  • Hexagon and Leica Geosystems AG/Switzerland
  • Unitron/Netherlands
  • ASML/Netherlands
  • Pentacom/Germany
  • Newtec/Germany
  • CineFlow/Canada
  • Xilinx/USA
  • TÜV/Netherlands


C, SystemVerilog, Linux, AMD and Intel FPGA and MPSoC, Yocto, OpenEmbedded, ARM, RISC-V, x86, PowerPC, PCI Express, Ultrascale+, GCC, GDB, U-Boot, SpinalHDL

2019 - 2021: Accelerated the dynamic partial reconfiguration


  • FPGA cryptocurrency miner, accelerate AMD FPGA PR/Dynamic Function Alveo U280
  • Accelerated the dynamic partial reconfiguration over SGDMA for X16R miner on U280 for lowest latency over PCIe.

2018 - 2018: Customer Training, Developing Linux Device Drivers for Xilinx

Customer: Hensoldt GmbH


  • Create and provide a three-day on-site customer training at Hensoldt Optronics GmBH, to learn their software teams to develop Linux device drivers for Xilinx Zynq designs.

2018 - 2018: Linux BSP

Customer: Xilinx Zynq 7040/Ultrascale+, Axon Digital Design


  • Schematic review, design changes, implemented board support package for PS, PL and around 15 external peripherals. Yocto build time optimizations using served state cache.

2017 - 2018: Linux BSP for NXP ARM i.MX7 with incremental OTA updates


  • Linux BSP for NXP ARM i.MX7 with incremental OTA updates
  • Define hardware and software architecture, develop Linux BSP and system software, use OSTree content-hash-based OTA delta upgrades, reproducible builds, Yocto, CI/CD.

2016 - 2018: Linux drivers and application reference design

Customer: Xilinx Inc/USA


  • Implemented a set of kernel drivers for HDMI and HDCP IP cores for the Video IP team of Xilinx, and a DMA reference design for the ZCU102 Ultrascale MPSoC/FPGA board.

2017 - 2017: PCI Express IP


Customer: Amazon Elastic Cloud 2 F1 FPGA instances


  • Licensed my product to be used in Amazon AWS ECS2 F1 as core technology between CPU and FPGA for cloud-based FPGA hardware accelerators for AI/ML/video coding.

2014 - 2017: Windows and Linux device drivers PCIe IP and HDMI IP

Customer: FPGA, Xilinx/USA


  • Developed Linux and Windows drivers for Xilinx PCIe (PG195), Xilinx? SDAccel OpenCL FPGA framework and HDMI 2.0 / HDCP. Trained Xilinx engineers on-site in San Jose.
  • Architecture advisor for Xiinx. Sold to Xilinx/USA in fixed-price projects.

2016 - 2016: Bluetooth Low Energy (BLE) Medical Wearable Device

Customer: NovioScan


  • All embedded software for dual-chip bare-metal (STM32L and Nordic NRF51), pushing ADC/DAC/PWM/DMA/SPI peripherals and BLE streaming bandwidth to their limits.

2016 - 2016: Linux Ubuntu kernel port

Customer: Gumxtix DuoVero COM


  • Ported Ubuntu kernel to Gumstix OMAP4 board, backported WiLink8 WiFi drivers, hardware-accelerated real-time H.264 video encoding to an iPhone app using RTP/WiFi.

2009 - 2016: Lancero and Vulcano Low Latency PCI Express Scatter-Gather DMA FPGA IP

Customer: drivers


  • I architected and implemented high performance Linux, QNX Neutrino and Windows device drivers and applications for, and co-designed the Lancero and Vulcano Low Latency PCI Express SGDMA FPGA IP cores.
  • Own IP/product.
  • Acquired, supported over 30 industrial customers with CPU/FPGA PCI Express designs; ARM, PowerPC, x86.

2012 - 2014: Multicamera panoramic lossless image encoder

Customer: The Netherlands


  • Developed architecture, Linux device driver and application for PowerPC and Intel CPUs.
  • Designed JPEG-LS lossless image compressor in FPGA SystemVerilog with testbench against a C model.
  • Achieves 100x speed-up acceleration compared to an Intel i7 CPU.

2012 - 2013: Automotive Embedded Linux device drivers

Customer: Bosch, Germany


  • Developed Linux device drivers for a custom FPGA USB High Speed eight-channel audio device of an automotive entertainment system.
  • Co-developed FPGA IP blocks.

2011 - 2011: Design of a energy prepay terminal, heating/cooling control, Spain


  • I realized the full hardware and software design for a human touch screen interface with Linux / Qt embedded software, based on Atmel SAM9G45 ARM microprocessor.

Further projects on request

Aus- und Weiterbildung

1995 ? 2006

Information Technology Sciences and in Electrical Engineering

MSc. degrees

University of Technology Eindhoven, Electrical Engineering

Key Focus:

  • Master thesis project on request


Started Engineering degree (ir.) Information Technology, then switched to MSc.

1986 ? 1992

Prep Science Education/VWO degree

Cobbenhagen College, Tilburg



FPGA Linux Embedded Yocto Xilinx Vivado SystemVerilog C Verilog VHDL STM32 Ethernet ModelSim Video over IP PCIe quartus

Produkte / Standards / Erfahrungen / Methoden

Personal Interest and drive

  • Strong interest in challenging projects involving Embedded Linux, C, Yocto, video, high performance, kernel, device drivers, PCIe, FPGA. Thorough experience and knowledge of complete vertical solution stack from on-chip hardware to software application layers.
  • I am interested in freelance consultancy, technical lead roles, or involvement in startups, for quality driven product development using innovative technologies. My preferred work place is at my own lab office, but depending on role I work on-site part-time. I work agile and pragmatic with a drive for quality and efficiency in all aspects of work.


1999 - 1999:

Role: Software Engineering Dep.

Customer: Signaal Communications (Thales)


  • Replaced a commercial real-time kernel by the open-source ?eCos? kernel and compared.

1998 ? 1999:

Role: Fac. of Electrical Engineering

Customer: University of Technology Eindhoven


  • Telecommunication Technology & Electromagnetism Group
  • Designed/implemented a communication protocol for 150 Mbit/s wireless radio LAN.


2005 - 2018:


  • OpenEmbedded/Yocto core developer since start of project. Board member (2014-2016).

2016 - 2016:


  • Linux kernel, Intel PCIe SGDMA device driver, Xilinx MPSoC video IP device drivers.

2010 - 2016:


  • Yocto project participating membership.

2010 - 2010:


  • ChibiOS/RT conditional variables support, board support.

2000 - 2009:


  • lwIP; Project leader for the lwIP lightweight TCP/IP stack project

2008 -2008:


  • Linux kernel, Intel PCIe SGDMA device driver, Xilinx MPSoC video IP device drivers.

2006 - 2006:


  • Fixes to Linux kernel PREEMPT_RT real-time support

2004 - 2004:


  • Micrium uCOS-II automotive processor port, prioritized pre-emptive interrupt support

Professional Strengths

  • System level risk assessment and good in agile risk-driven development.
  • Root cause analysis, I want to really solve problems, not work around them.
  • Can teach complex concepts in simple manners, training juniors.
  • Highly experienced with concurrent/parallel processing software and FPGA RTL.
  • Targeting high quality, long term value, favoring the end-user perspective.

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