2021 - 2023: Implemented Wireguard VPN protocol

Role: Principal Systems Architect

Customer: BrightAI B.V., Full Remote, Switzerland, The Netherlands

Tasks:

• Implemented Wireguard VPN protocol in FPGA for 100 Gbit/s SmartNIC on AMD Alveo U50. Architect and lead small team, code implementation. Vivado SpinalHDL, SystemVerilog, C, Rust, VexRiscv, RISC-V, Verilator, GHDL, CocoTB, SpinalSim, CI/CD.

2008 - 2023: Helped approx. 70 high-tech companies

Role: Embedded Systems Consultant

Customer: on request, Eindhoven, The Netherlands

Tasks:

• Helped approx. 70 high-tech companies. Define CPU, SoC, GPU, FPGA system architectures (COTS/custom hardware, RTL firmware, open-source, proprietary software), make trade-offs, select hardware components, open-source software, implement board support software, FPGA firmware, kernel ports, device drivers, middleware and applications.
• I work remotely in own office and lab spaces, fixed price or on hourly tarif.

Developed own products portfolio

• Come up with, design, develop, sell and provide intellectual property and support.
• Lancero PCI Express SGDMA PCIe for Intel FPGA which is the background technology for Amazon AWS ECS F1 FPGA acceleration.
• JPEG-LS Lossless image compressor for AMD/Intel FPGA?s,
• i.MX53/Cyclone V industrial camera reference design.

Customers

• Some of my direct customers include Cymer/USA, ASML/Netherlands
• Robert Bosch Car Multimedia GmbH/Germany
• Philips Innovation Services/Netherlands
• National Institute of Standards and Technology/USA
• Hexagon and Leica Geosystems AG/Switzerland
• Unitron/Netherlands
• ASML/Netherlands
• Pentacom/Germany
• Newtec/Germany
• CineFlow/Canada
• Xilinx/USA
• TÜV/Netherlands

Skills:

C, SystemVerilog, Linux, AMD and Intel FPGA and MPSoC, Yocto, OpenEmbedded, ARM, RISC-V, x86, PowerPC, PCI Express, Ultrascale+, GCC, GDB, U-Boot, SpinalHDL

Tasks:

• FPGA cryptocurrency miner, accelerate AMD FPGA PR/Dynamic Function Alveo U280
• Accelerated the dynamic partial reconfiguration over SGDMA for X16R miner on U280 for lowest latency over PCIe.

2018 - 2018: Customer Training, Developing Linux Device Drivers for Xilinx

Customer: Hensoldt GmbH

Tasks:

• Create and provide a three-day on-site customer training at Hensoldt Optronics GmBH, to learn their software teams to develop Linux device drivers for Xilinx Zynq designs.

2018 - 2018: Linux BSP

Customer: Xilinx Zynq 7040/Ultrascale+, Axon Digital Design

Tasks:

• Schematic review, design changes, implemented board support package for PS, PL and around 15 external peripherals. Yocto build time optimizations using served state cache.

2017 - 2018: Linux BSP for NXP ARM i.MX7 with incremental OTA updates

Tasks:

• Linux BSP for NXP ARM i.MX7 with incremental OTA updates
• Define hardware and software architecture, develop Linux BSP and system software, use OSTree content-hash-based OTA delta upgrades, reproducible builds, Yocto, CI/CD.

Customer: Xilinx Inc/USA

Tasks:

• Implemented a set of kernel drivers for HDMI and HDCP IP cores for the Video IP team of Xilinx, and a DMA reference design for the ZCU102 Ultrascale MPSoC/FPGA board.

Role:

Customer: Amazon Elastic Cloud 2 F1 FPGA instances

Tasks:

• Licensed my product to be used in Amazon AWS ECS2 F1 as core technology between CPU and FPGA for cloud-based FPGA hardware accelerators for AI/ML/video coding.

Customer: FPGA, Xilinx/USA

Tasks:

• Developed Linux and Windows drivers for Xilinx PCIe (PG195), Xilinx? SDAccel OpenCL FPGA framework and HDMI 2.0 / HDCP. Trained Xilinx engineers on-site in San Jose.
• Architecture advisor for Xiinx. Sold to Xilinx/USA in fixed-price projects.

Customer: NovioScan

Tasks:

• All embedded software for dual-chip bare-metal (STM32L and Nordic NRF51), pushing ADC/DAC/PWM/DMA/SPI peripherals and BLE streaming bandwidth to their limits.

Customer: Gumxtix DuoVero COM

Tasks:

• Ported Ubuntu kernel to Gumstix OMAP4 board, backported WiLink8 WiFi drivers, hardware-accelerated real-time H.264 video encoding to an iPhone app using RTP/WiFi.

2009 - 2016: Lancero and Vulcano Low Latency PCI Express Scatter-Gather DMA FPGA IP

Customer: drivers

Tasks:

• I architected and implemented high performance Linux, QNX Neutrino and Windows device drivers and applications for, and co-designed the Lancero and Vulcano Low Latency PCI Express SGDMA FPGA IP cores.
• Own IP/product.
• Acquired, supported over 30 industrial customers with CPU/FPGA PCI Express designs; ARM, PowerPC, x86.

Customer: The Netherlands

Tasks:

• Developed architecture, Linux device driver and application for PowerPC and Intel CPUs.
• Designed JPEG-LS lossless image compressor in FPGA SystemVerilog with testbench against a C model.
• Achieves 100x speed-up acceleration compared to an Intel i7 CPU.

2012 - 2013: Automotive Embedded Linux device drivers

Customer: Bosch, Germany

Tasks:

• Developed Linux device drivers for a custom FPGA USB High Speed eight-channel audio device of an automotive entertainment system.
• Co-developed FPGA IP blocks.

Tasks:

• I realized the full hardware and software design for a human touch screen interface with Linux / Qt embedded software, based on Atmel SAM9G45 ARM microprocessor.